Patent classifications
H03B1/04
RADAR TRANSCEIVER WITH PHASE NOISE CANCELLATION
A method for cancelling phase noise in a radar signal is described herein. In accordance with one embodiment, the method includes transmitting an RF oscillator signal, which represents a local oscillator signal including phase noise, to a radar channel and receiving a respective first RF radar signal from the radar channel. The first RF radar signal included at least one radar echo of the transmitted RF oscillator signal. Further, the method includes applying the RF oscillator signal to an artificial radar target composed of circuitry, which applies a delay and a gain to the RF oscillator signal, to generate a second RF radar signal. The second RF radar signal is modulated by a modulation signal thus generating a frequency-shifted RF radar signal. Further, the method includes subtracting the frequency-shifted RF radar signal from the first RF radar signal.
VOLTAGE CONTROLLED OSCILLATORS WITH HARMONIC REJECTION
An oscillator apparatus includes: a voltage controlled oscillator that generates an oscillator output including a fundamental frequency, wherein the fundamental frequency is a function of a tuning voltage; and a tunable filter that receives the oscillator output and provides a filtered oscillator output, wherein the tunable filter has a frequency characteristic that suppresses a harmonic of the fundamental frequency, the frequency characteristic being a function of the tuning voltage.
Audio clocking apparatus, system, and method
Aspects of the present disclosure involve an audio clocking device including high-frequency crystal oscillators capable of consistent low jitter and phase noise. The audio clocking device ensures that any low-jitter and low-noise signals are maintained as the signal propagates through circuitry of the audio clocking device.
Audio clocking apparatus, system, and method
Aspects of the present disclosure involve an audio clocking device including high-frequency crystal oscillators capable of consistent low jitter and phase noise. The audio clocking device ensures that any low-jitter and low-noise signals are maintained as the signal propagates through circuitry of the audio clocking device.
HIGH FREQUENCY INTEGRATED CIRCUIT AND EMITTING DEVICE FOR IRRADIATING THE INTEGRATED CIRCUIT
What is described is a high-frequency integrated circuit provided on a III-V compound semiconductor, wherein an emitting device is radiation-coupled with the integrated circuit such that the emitting device irradiates the integrated circuit, and wherein the integrated circuit has at least one of an oscillator, a mixer, a phase shifter, a frequency divider or an amplifier.
HIGH FREQUENCY INTEGRATED CIRCUIT AND EMITTING DEVICE FOR IRRADIATING THE INTEGRATED CIRCUIT
What is described is a high-frequency integrated circuit provided on a III-V compound semiconductor, wherein an emitting device is radiation-coupled with the integrated circuit such that the emitting device irradiates the integrated circuit, and wherein the integrated circuit has at least one of an oscillator, a mixer, a phase shifter, a frequency divider or an amplifier.
Reference clock frequency correction by mixing with digitally-controlled low-frequency compensation signal
A system for reference clock frequency correction is described. The system comprises a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, wherein the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (iii) output the generated compensation signal. The system further comprises a mixer block configured to (i) receive, as input, the generated compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft-switching method to reduce the effect of quantization noise is further described.
Reference clock frequency correction by mixing with digitally-controlled low-frequency compensation signal
A system for reference clock frequency correction is described. The system comprises a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) generate a compensation signal based on the oscillator signal and the one or more control signals, wherein the generated compensation signal is a discretized sinusoidal signal having a controllable frequency, and (iii) output the generated compensation signal. The system further comprises a mixer block configured to (i) receive, as input, the generated compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the generated compensation signal with the oscillator signal. A soft-switching method to reduce the effect of quantization noise is further described.
METHOD AND APPARATUS FOR RECONFIGURABLE MULTICORE OSCILLATOR
The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.
METHOD AND APPARATUS FOR RECONFIGURABLE MULTICORE OSCILLATOR
The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.