A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

A flash memory is a memory element that stores a trimming code for adjusting a resistance value of a trimming resistor so that an oscillation frequency of an output clock signal generated by a CR oscillator circuit becomes a preset frequency. The CR oscillator circuit generates the output clock signal having a frequency based on a time constant determined by a resistance value of the trimming resistor being a resistive element, and a capacitance value of a capacitive element. An up-down counter is a counter circuit that, in synchronization with the output clock signal generated by the CR oscillator circuit, increases or decreases the trimming code stored in the flash memory, and outputs the trimming code as a trimming code for adjusting the resistance value of the trimming resistor.

A flash memory is a memory element that stores a trimming code for adjusting a resistance value of a trimming resistor so that an oscillation frequency of an output clock signal generated by a CR oscillator circuit becomes a preset frequency. The CR oscillator circuit generates the output clock signal having a frequency based on a time constant determined by a resistance value of the trimming resistor being a resistive element, and a capacitance value of a capacitive element. An up-down counter is a counter circuit that, in synchronization with the output clock signal generated by the CR oscillator circuit, increases or decreases the trimming code stored in the flash memory, and outputs the trimming code as a trimming code for adjusting the resistance value of the trimming resistor.

Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.

Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

A current mode sinusoidal oscillator includes a current amplifier with distinct current input and four output terminals. The amplifier includes a current input terminal X, a first and a second negative current feedback terminals I.sub.fo1 and I.sub.fo2, along with a positive current output terminal I.sub.op and a negative current output terminal I.sub.on. The oscillator is characterized by a first feedback path that transmits a portion of a current at the first negative current feedback terminal I.sub.fo1 to the current input terminal X of the oscillator. Additionally, a second feedback path, interlinking I.sub.fo2 and X, comprises a three-stage phase lag network designed to confer a phase shift of negative 180 degrees to the current signal at a frequency of oscillation determined by capacitor and resistor values of the three-stage phase lag network. A load is connected between I.sub.op and I.sub.on, which receives the sinusoidal current at the frequency of oscillation.

A current mode sinusoidal oscillator includes a current amplifier with distinct current input and four output terminals. The amplifier includes a current input terminal X, a first and a second negative current feedback terminals I.sub.fo1 and I.sub.fo2, along with a positive current output terminal I.sub.op and a negative current output terminal I.sub.on. The oscillator is characterized by a first feedback path that transmits a portion of a current at the first negative current feedback terminal I.sub.fo1 to the current input terminal X of the oscillator. Additionally, a second feedback path, interlinking I.sub.fo2 and X, comprises a three-stage phase lag network designed to confer a phase shift of negative 180 degrees to the current signal at a frequency of oscillation determined by capacitor and resistor values of the three-stage phase lag network. A load is connected between I.sub.op and I.sub.on, which receives the sinusoidal current at the frequency of oscillation.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.