A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

An offset-mixer INSO provides a fixed phase shift in the reference arm of the interferometric bridge to align the reference arms' variable phase shifter to the mixer's I-channel output and uses the variable phase shifter to amplitude balance the reference and reflection arms. A difference signal between the mixer's Q-channel output and an externally applied carrier frequency tuning voltage V.sub.PLL is applied to an amplification network to provide the control signal to the loop phase shifter to adjust the carrier frequency. Elimination of the variable attenuator and rotation of the variable phase shifter eliminates and reduces their respective phase noise contributions such that the dominant phase noise source is now the mixer.

An offset-mixer INSO provides a fixed phase shift in the reference arm of the interferometric bridge to align the reference arms' variable phase shifter to the mixer's I-channel output and uses the variable phase shifter to amplitude balance the reference and reflection arms. A difference signal between the mixer's Q-channel output and an externally applied carrier frequency tuning voltage V.sub.PLL is applied to an amplification network to provide the control signal to the loop phase shifter to adjust the carrier frequency. Elimination of the variable attenuator and rotation of the variable phase shifter eliminates and reduces their respective phase noise contributions such that the dominant phase noise source is now the mixer.

An oscillator includes a power supply terminal, a ground terminal, a positive-side clock terminal, and a negative-side clock terminal. The power supply terminal is supplied with a high potential-side power supply voltage. The ground terminal is supplied with a low potential-side power supply voltage. The positive-side clock terminal outputs a positive-side clock signal of a differential clock signal. The negative-side clock terminal outputs a negative-side clock signal of the differential clock signal. The power supply terminal and the ground terminal are arranged side by side, and the positive-side clock terminal and the negative-side clock terminal are arranged side by side.

An oscillator includes a power supply terminal, a ground terminal, a positive-side clock terminal, and a negative-side clock terminal. The power supply terminal is supplied with a high potential-side power supply voltage. The ground terminal is supplied with a low potential-side power supply voltage. The positive-side clock terminal outputs a positive-side clock signal of a differential clock signal. The negative-side clock terminal outputs a negative-side clock signal of the differential clock signal. The power supply terminal and the ground terminal are arranged side by side, and the positive-side clock terminal and the negative-side clock terminal are arranged side by side.