An oscillator circuit includes an amplifying unit and a first feedback resistor. The amplifying unit includes an inverter at an input stage being connected to the one end of a crystal resonator, an inverter at an output stage being connected to the other end of the crystal resonator, and a linear amplifier. The linear amplifier is connected between an output terminal of the inverter at the input stage and an input terminal of the inverter at the output stage. The linear amplifier includes at least one inverter and a second feedback resistor. The second feedback resistor is connected in parallel to the at least one inverter. The linear amplifier has a conductance with a magnitude larger than a conductance of the inverter at the input stage and equal to or less than a conductance of the inverter at the output stage.

Embodiments may relate to a structure to be used in a neural network. A first column and a second column, both of which are to couple with a substrate. A capacitor structure may be electrically coupled with the first column. An insulator-metal transition (IMT) structure may be coupled with the first column such that the capacitor structure is electrically positioned between the IMT structure and the first column. A resistor structure may further be electrically coupled with the IMT structure and the second column such that the resistor structure is electrically positioned between the second column and the IMT structure. Other embodiments may be described or claimed.

Embodiments may relate to a structure to be used in a neural network. A first column and a second column, both of which are to couple with a substrate. A capacitor structure may be electrically coupled with the first column. An insulator-metal transition (IMT) structure may be coupled with the first column such that the capacitor structure is electrically positioned between the IMT structure and the first column. A resistor structure may further be electrically coupled with the IMT structure and the second column such that the resistor structure is electrically positioned between the second column and the IMT structure. Other embodiments may be described or claimed.

Accordingly the embodiments herein provide a method for fabricating a neuron oscillator (200a). The neuron oscillator (200a) includes a thermal insulating device connected with a resistor and a capacitor in series to produce self-sustained oscillations, where the resistor and the capacitor are arranged in parallel manner. The neuron oscillator (200a) eliminates a requirement of an additional compensation circuitry for a consistent performance over a time under heating issues. Additionally, an ON/OFF ratio of the neuron oscillator (200a) improves to a broader resistor range. Further, a presence of tunable synaptic memristor functionality of the neuron oscillator (200a) provides a reduced fabrication complexity to a large scale ONN. An input voltage required for the neuron oscillator (200a) is low (2-3 V) which makes it suitable to use with existing circuitries without using any additional converters. Additionally, an amplitude of the oscillations is a significant fraction of an applied bias which eliminates a need for an amplification.

Accordingly the embodiments herein provide a method for fabricating a neuron oscillator (200a). The neuron oscillator (200a) includes a thermal insulating device connected with a resistor and a capacitor in series to produce self-sustained oscillations, where the resistor and the capacitor are arranged in parallel manner. The neuron oscillator (200a) eliminates a requirement of an additional compensation circuitry for a consistent performance over a time under heating issues. Additionally, an ON/OFF ratio of the neuron oscillator (200a) improves to a broader resistor range. Further, a presence of tunable synaptic memristor functionality of the neuron oscillator (200a) provides a reduced fabrication complexity to a large scale ONN. An input voltage required for the neuron oscillator (200a) is low (2-3 V) which makes it suitable to use with existing circuitries without using any additional converters. Additionally, an amplitude of the oscillations is a significant fraction of an applied bias which eliminates a need for an amplification.

A system for transmitting power and data through a two pin connection interface may have a first device having a power source, a first microcontroller with a first communication peripheral coupled with a first pin and a first control port coupled with a gate of a first MOSFET whose switch path couples the power source with the first pin; and a second device having a battery, a second microcontroller with a second communication peripheral coupled with a first pin and a second control port coupled with a gate of a second MOSFET whose switch path couples the battery with the first pin of the second device. When the devices are coupled, the MOSFETs are synchronously turned on and off, wherein during an off-cycle a data transfer between the first and second device takes place through the first and second communication peripherals of the first and second device, respectively.

Some aspects of the present disclosure relate to detection of a Phase Hit and, upon detecting the Phase Hit, determining the magnitude and location of the Phase Hit. Detecting the Phase Hit may involve comparing a phase offset difference for successive pilot symbol to a detection threshold. Determination of the detection threshold may involve a Neyman-Pearson binary hypothesis testing (NP-BHT) approach. Once the magnitude and location of the Phase Hit are known, data symbols received after the location may be processed to remove the magnitude of the Phase Hit.

Some aspects of the present disclosure relate to detection of a Phase Hit and, upon detecting the Phase Hit, determining the magnitude and location of the Phase Hit. Detecting the Phase Hit may involve comparing a phase offset difference for successive pilot symbol to a detection threshold. Determination of the detection threshold may involve a Neyman-Pearson binary hypothesis testing (NP-BHT) approach. Once the magnitude and location of the Phase Hit are known, data symbols received after the location may be processed to remove the magnitude of the Phase Hit.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.

In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.