Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

Systems and methods are provided for generating reference signals with high interference immunity. A signal source may generate reference signals having a particular reference frequency based on characteristics of the source of the reference signals, for use in driving at least one component in a system. One or more processing may then process the generated reference signals, based on particular frequency positions relative to the particular reference frequency and other operations and/or components of the system. The processing may include filtering at the particular frequency positions. The particular frequency positions may correspond to the harmonics positions of the particular reference frequency. The signal source may be a crystal oscillator.

A system includes a signal generator and a signal combiner. The signal generator is configured to output a first signal having a first frequency and to output one or more signals having the first frequency and having phases shifted relative to the first signal by predetermined amounts. The signal combiner is configured to combine the first signal and the one or more signals to output a frequency multiplied second signal having a second frequency. The second frequency is greater than the first frequency.

A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width. The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

Disclosed is a clock system for generating an error-reduced clock output. In one implementation, the clock system includes a plurality of physical clusters of MEMS oscillators that provide a set of associated clock inputs to a processor. The processor performs RMS error correction and/or Kalman filtering and/or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. In another implementation, the processor configures the MEMS oscillators into a dynamic plurality of logical clusters instead of relying on a plurality of physical clusters. The processor performs RMS error correction and/or Kalman filtering and/or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. Also disclosed are techniques for compensating for errors related to temperature drift, tilt, and age drift of the MEMS oscillators.

Disclosed is a clock system for generating an error-reduced clock output. In one implementation, the clock system includes a plurality of physical clusters of MEMS oscillators that provide a set of associated clock inputs to a processor. The processor performs RMS error correction and/or Kalman filtering and/or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. In another implementation, the processor configures the MEMS oscillators into a dynamic plurality of logical clusters instead of relying on a plurality of physical clusters. The processor performs RMS error correction and/or Kalman filtering and/or Bayesian particle filtering to generate an oscillator control output to adjust a frequency of a controlled MEMS oscillator to generate the error-reduced clock output. Also disclosed are techniques for compensating for errors related to temperature drift, tilt, and age drift of the MEMS oscillators.

Techniques for reducing harmonics of a local oscillator (LO) signal. A methodology implementing the techniques according to an embodiment includes splitting an LO signal into first and second LO signals using a passive splitting circuit. The method also includes generating one of either a first enable signal or a second enable signal based on the LO signal frequency. The method further includes amplifying and filtering the first LO signal to generate a first band LO signal, in response to the first enable signal, and amplifying and filtering the second LO signal to generate a second band LO signal, in response to the second enable signal. The method further includes combining, using a passive Wilkinson combiner, output paths of the first band processing circuit and the second band processing circuit to provide either the first band LO signal or the second band LO signal as a reduced harmonic LO signal.