A demodulator circuit receives an envelope signal for comparison against a switched reference signal that is generated as a function of the envelope signal and as a function of an output signal of the demodulator circuit. The switched reference signal is filtered by an RC filter prior to comparison. The output signal is dependent on a difference between the filtered switched reference signal and the envelope signal.

An electronic device may be provided with an antenna, a receiver, and baseband circuitry coupled to the receiver over a digital interface. The receiver may receive radio-frequency signals using the antenna and may generate digital in-phase and quadrature-phase (I/Q) samples from the radio-frequency signals. The I/Q samples may have a bit width and may be transmitted to the baseband circuitry over the digital interface. The baseband circuitry may evaluate a radio condition of the receiver based on the I/Q samples. The baseband circuitry may adjust the bit width of the I/Q samples based on the radio condition. For example, the baseband circuitry may decrease the bit width when wireless performance metric data falls below a threshold and/or may increase the bit width when the wireless performance metric data exceeds a threshold. This may minimize power consumed by the digital interface without sacrificing wireless performance.

A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately /2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.

A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately /2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.

A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.

Systems and methods for synchronous demodulation using passive sampled analog filtering are disclosed. A system for synchronous demodulation includes an input channel for accepting an input signal, a first passive sampled analog filter for filtering the input signal, a mixer for mixing the filtered input signal and outputting a mixed signal, a second passive sampled analog filter for filtering the mixed signal, and an output channel for outputting the filtered mixed signal.

Systems and methods for synchronous demodulation using passive sampled analog filtering are disclosed. A system for synchronous demodulation includes an input channel for accepting an input signal, a first passive sampled analog filter for filtering the input signal, a mixer for mixing the filtered input signal and outputting a mixed signal, a second passive sampled analog filter for filtering the mixed signal, and an output channel for outputting the filtered mixed signal.

A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna.

Techniques related to signal processing include setting up a first operation mode or a second operation mode. In the first operation mode: providing a first analog signal to a first A/D converter by a first switch and a second analog signal to a second A/D by second switch, and converting the first analog signal to a first digital signal by the first A/D and the second analog signal to a second digital signal by the second A/D. In the second operation mode: demodulating a third analog signal to an in-phase signal and a quadrature signal by an I-Q-demodulator, providing the in-phase signal to the first A/D by the first switch, providing the quadrature signal to a second A/D by second switch, converting the in-phase signal to a third digital signal by the first A/D, and converting the quadrature signal to a fourth digital signal by the second A/D.

Techniques related to signal processing include setting up a first operation mode or a second operation mode. In the first operation mode: providing a first analog signal to a first A/D converter by a first switch and a second analog signal to a second A/D by second switch, and converting the first analog signal to a first digital signal by the first A/D and the second analog signal to a second digital signal by the second A/D. In the second operation mode: demodulating a third analog signal to an in-phase signal and a quadrature signal by an I-Q-demodulator, providing the in-phase signal to the first A/D by the first switch, providing the quadrature signal to a second A/D by second switch, converting the in-phase signal to a third digital signal by the first A/D, and converting the quadrature signal to a fourth digital signal by the second A/D.