Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

A lock-in amplifier includes a clock signal generator configured to generate a first demodulation clock signal and a second demodulation clock signal having a phase difference of 90 degrees and a same demodulation frequency; and a detector configured to, based on an input signal, the first demodulation clock signal, and the second demodulation clock signal, provide an offset voltage corresponding to an offset of the lock-in amplifier in a first operation mode, and provide a first output voltage and a second output voltage, each of which correspond to a demodulation frequency component of the input signal in a second operation mode.

A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.

A demodulation device includes a phase rotation module, a phase adjustment module, a phase comparison module, and a reference signal generation module. The phase rotation module rotates phases of an I-Phase signal and a Q-Phase signal in a received signal of a multilevel PSK signal using a reference signal. The phase adjustment module adjusts the phases of the phase rotated I-Phase signal and the phase rotated Q-Phase signal output from the phase rotation module by multiplying the phases of the I-Phase signal and the Q-Phase signal with an integer value to generate a phase adjusted I-Phase signal and a phase adjusted Q-Phase signal. The phase comparison module compares the phase of the phase adjusted I-Phase signal with the phase of the phase adjusted Q-Phase signal to generate a phase comparison result. Also, the reference signal generation module generates a reference signal using the phase comparison result.

A quadrature demodulator not requiring analogue mixers. The demodulation is made using a first integrator and a second integrator which are controlled by square logic signals at twice the frequency of the carrier, the received signal being alternatively integrated by the first integrator and the second integrator over periods of time equal to a quarter period of time of the carrier frequency. The samples of the first and second integrators are sampled and subtracted from each other. The successive samples are combined in a first and a second combining module for providing in-phase and quadrature component samples. This demodulator can further be provided with a synchronization module IQ and a symbol synchronization module.

A signal detection circuit includes: a VCO that generates a reference signal; a complex signal generation circuit that generates a complex signal from an input signal and the reference signal; a vector operation circuit that calculates an argument of the complex signal by performing a vector operation; and a subtracting phase comparator that compares the argument with a phase of the reference signal by calculating a difference between the argument and the phase of the reference signal, wherein the complex signal generation circuit includes: a multiplication circuit that multiplies the input signal by the reference signal; and an HPF that removes a DC component from a signal output from the multiplication circuit.