A very low intermediate frequency (VLIF) receiver and a method of controlling a VLIF receiver. The method comprises estimating energy levels in first and second signals and detecting interference from a first adjacent channel interferer based upon a difference in energy in the first and second signals. The first signal comprising a first on-channel portion and an adjacent channel portion and the second signal comprises an intermediate frequency translation of the first on-channel portion. The energy levels are estimated for corresponding time instances and the adjacent channel interferer is of the adjacent channel portion. The VLIF receiver is then controlled based upon the detected interference.

A very low intermediate frequency (VLIF) receiver and a method of controlling a VLIF receiver. The method comprises estimating energy levels in first and second signals and detecting interference from a first adjacent channel interferer based upon a difference in energy in the first and second signals. The first signal comprising a first on-channel portion and an adjacent channel portion and the second signal comprises an intermediate frequency translation of the first on-channel portion. The energy levels are estimated for corresponding time instances and the adjacent channel interferer is of the adjacent channel portion. The VLIF receiver is then controlled based upon the detected interference.

A heterodyne receiver structure comprises a frequency conversion block arranged to convert an incoming analog radio frequency (RF) signal to an analog intermediate frequency (IF) signal; a filter block arranged to filter said analog IF signal; and an analog-to-digital (AD) converter block arranged to convert said filtered analog IF signal to a digital signal, wherein the AD converter block (309) is arranged to convert the filtered analog IF signal to the digital signal by using a sampling frequency (fs) which is at least N times a maximum bandwidth of the filtered analog IF signal, wherein the frequency spectrum from zero to the sampling frequency is divided into N frequency zones of equal width, wherein N is an even positive number higher than two; the frequency conversion block (304) is arranged to convert the incoming analog RF signal to the analog IF signal such that the analog IF signal is located in any of the N/2-1 frequency zones having lowest frequency; and the filter block (306-308) is arranged to low pass the analog IF signal such that any disturbing signal located in a zone, which would have a mirror image after the AD conversion in the zone, in which the analog IF signal is located, is filtered away, wherein the heterodyne receiver structure further comprises a digital signal processing block (311) arranged to filter said digital signal.

A heterodyne receiver structure comprises a frequency conversion block arranged to convert an incoming analog radio frequency (RF) signal to an analog intermediate frequency (IF) signal; a filter block arranged to filter said analog IF signal; and an analog-to-digital (AD) converter block arranged to convert said filtered analog IF signal to a digital signal, wherein the AD converter block (309) is arranged to convert the filtered analog IF signal to the digital signal by using a sampling frequency (fs) which is at least N times a maximum bandwidth of the filtered analog IF signal, wherein the frequency spectrum from zero to the sampling frequency is divided into N frequency zones of equal width, wherein N is an even positive number higher than two; the frequency conversion block (304) is arranged to convert the incoming analog RF signal to the analog IF signal such that the analog IF signal is located in any of the N/2-1 frequency zones having lowest frequency; and the filter block (306-308) is arranged to low pass the analog IF signal such that any disturbing signal located in a zone, which would have a mirror image after the AD conversion in the zone, in which the analog IF signal is located, is filtered away, wherein the heterodyne receiver structure further comprises a digital signal processing block (311) arranged to filter said digital signal.