Patent classifications
H03F1/02
Radio frequency amplifier implementing an input baseband enhancement circuit and a process of implementing the same
An amplifier includes an input matching network; at least one transistor; an input lead coupled to the at least one transistor; a ground terminal coupled to the transistor; an output lead coupled to the at least one transistor; an output matching circuit coupled to the output lead and to the at least one transistor; and a baseband impedance enhancement circuit having at least one reactive element coupled to the input matching network. The baseband impedance enhancement circuit is configured to reduce resonances of a baseband termination.
Audio power source with improved efficiency
One example includes a differential amplifier, a voltage weighting element, coupled to a voltage source which provides an input voltage, to provide a reference voltage with a constant power limit when the input voltage varies, an error amplifier configured to receive and compare the reference voltage provided from the voltage weighting element and a feedback sensed voltage provided from the differential amplifier to identify whether the sensed voltage exceeds the reference voltage, and a pulse width modulation (PWM) controller, coupled to a power transformer and the error amplifier, that reduces a transformer input current provided to the power transformer based on the comparison of the reference voltage from the voltage weighting element and the feedback sensed voltage from the differential amplifier.
Signal processing circuit for reducing ripple in an output signal of a spinning current hall sensor and signal processing method
Signal processing circuit for a Hall sensor and signal processing method. Signal processing circuits for four-phase spinning Hall magnetic field sensors, corresponding methods and corresponding magnetic field sensor apparatuses are provided. In this case, a correction signal (c) is generated on the basis of a first feedback signal (fb1) and a second feedback signal (fb2), wherein the first feedback signal (fb1) is provided with a shorter signal propagation time than the second feedback signal (fb2).
Signal processing circuit for reducing ripple in an output signal of a spinning current hall sensor and signal processing method
Signal processing circuit for a Hall sensor and signal processing method. Signal processing circuits for four-phase spinning Hall magnetic field sensors, corresponding methods and corresponding magnetic field sensor apparatuses are provided. In this case, a correction signal (c) is generated on the basis of a first feedback signal (fb1) and a second feedback signal (fb2), wherein the first feedback signal (fb1) is provided with a shorter signal propagation time than the second feedback signal (fb2).
Power amplifier with a power transistor and an electrostatic discharge protection circuit on separate substrates
An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.
Dual-Mode Power Amplifier For Wireless Communication
In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.
AI-ASSISTED POWER AMPLIFIER OPTIMIZATION
A compensator compensates for the distortions of a power amplifier circuit. A power amplifier neural network (PAN) is trained to model the power amplifier circuit using pre-determined input and output signal pairs that characterize the power amplifier circuit. Then a compensator is trained to pre-distort a signal received by the PAN. The compensator uses a neural network trained to optimize a loss between a compensator input and a PAN output, and the loss is calculated according to a multi-objective loss function that includes one or more time-domain loss function and one or more frequency-domain loss functions. The trained compensator performs signal compensation to thereby output a pre-distorted signal to the power amplifier circuit.
Power amplification system with adjustable common base bias
Power amplification system with adjustable common base bias. A power amplification system can include a cascode amplifier coupled to a radio-frequency input signal and coupled to a radio-frequency output. The power amplification system can further include a biasing component configured to apply one or more biasing signals to the cascode amplifier, the biasing component including a bias controller and one or more bias components. Each respective bias component may be coupled to a respective bias transistor.
Amplifier having envelope control
In some embodiments, an amplifier system can include an amplifier circuit having first and second amplifiers configured to amplify respective first and second portions of an input signal. Each of the first and second amplifiers can include a cascode stage with input and output transistors arranged in a cascode configuration. The amplifier system can further include an envelope tracking bias circuit coupled to the amplifier circuit and configured to provide a bias signal to the output transistor of the cascode stage of at least one of the first and second amplifiers. The amplifier system can further include a supply circuit configured to provide a non-envelope tracking supply voltage to the output transistor of the cascode stage of the at least one of the first and second amplifiers.
Amplifier biasing techniques
Techniques for biasing output transistor of a push-pull amplifier output stage are provided. In certain applications the techniques can improve efficiency of the amplifier. In an example, a circuit can include an output stage including first and second output transistors, a first scaled replica transistor corresponding to the first output transistor, and an amplifier circuit in a feedback arrangement for biasing a gate of the first output transistor at a level that, at a specified stand-by current level of the first output transistor, reproduces a voltage difference between the drain and source terminals of the first output transistor across the drain and source terminals of the first replica transistor.