A filter device configured to directly connect to a differential power amplifier of a transmit chain circuit. The filter device may include a transformer and a filter configured as a half lattice equivalent topology and having a single-ended output. The filter may be a lattice filter configured as a full lattice topology or a lattice equivalent filter configured as a half lattice equivalent topology. The filter includes a first branch having a first impedance network of one or more first impedance elements and a second branch having a second impedance network of one or more second impedance elements. The single-ended output of the filter device may connect to an antenna switch that is in turn connected to an antenna.

An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

A Doherty power amplifier comprising: an input configured to receive an input signal to be amplified and to split the input signal into a first portion and a second portion, the input signal having an operating frequency; a carrier amplifier path coupled to the input to receive the first portion, the carrier amplifier path including a carrier amplifier coupled to a differential inverter, the carrier amplifier being configured to amplify the first portion and provide an amplified first portion to the differential inverter, the differential inverter having a capacitance configured to make the differential inverter behave as a short circuit at odd harmonics of the operating frequency, the capacitance coupling a first path and a second path of the differential inverter in parallel; and a peaking amplifier path coupled to the input to receive the second portion and comprising a peaking amplifier configured to amplify the second portion.

Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

Disclosed herein are transconductance circuits, as well as related methods and devices. In some embodiments, a transconductance circuit may include an amplifier having a first input coupled to a voltage input of the transconductance circuit, and a switch coupled between an output of the amplifier and a second input of the amplifier.

Fast envelope tracking systems are provided herein. In certain embodiments, an envelope tracking system for a power amplifier includes a switching regulator and a differential error amplifier configured to operate in combination with one another to generate a power amplifier supply voltage for the power amplifier based on an envelope of a radio frequency (RF) signal amplified by the power amplifier. The envelope tracking system further includes a differential envelope amplifier configured to amplify a differential envelope signal to generate a single-ended envelope signal that changes in relation to the envelope of the RF signal. Additionally, the differential error amplifier generates an output current operable to adjust a voltage level of the power amplifier supply voltage based on comparing the single-ended envelope signal to a reference signal.

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

A power amplifier circuit includes a current generator and a current mirror driver. The current generator has a first input connected to a first voltage supply and an output configured to generate a first current. The current generator includes a first transistor, a second transistor, a first resistor and a second resistor. The first transistor has an emitter connected to ground. The second transistor has a base connected to a base of the first transistor and an emitter connected to ground. The first resistor is connected between the first voltage supply and a collector of the first transistor. The second resistor is connected between the first voltage supply and a collector of the second transistor. The current mirror drive has a first input connected to the output of the current generator to receive the first current and an output configured to generate a second current.