A high frequency signal amplifying circuitry of an embodiment includes a first splitter, a first amplifier, a second amplifier, a loop oscillation suppressor, and a combiner. The first amplifier includes a second splitter, a first carrier amplifier, a first peak amplifier, and a first combiner. The second amplifier includes a third splitter, a second carrier amplifier, a second peak amplifier, and a second combiner. The second carrier amplifier being adjacent to an associated the first carrier amplifier or the second peak amplifier being adjacent to an associated the first peak amplifier. The loop oscillation suppressor located between the second carrier amplifier and the associated first carrier amplifier or the second peak amplifier and the associated first peak amplifier.

The invention discloses a broadband logarithmic detector with high dynamic range, comprising a low noise amplifier, a compensate detection unit, a current summation and driving unit, an N-stage clipper amplifier and an N-stage detection unit. The invention improves the detection sensibility of the overall detector by adding a low noise amplifier before the first-stage clipper amplifier and extends the dynamic detection range of the overall detector through combination of the low noise amplifier and the compensate detection unit.

A front-end amplifier circuit for receiving a biological signal includes a signal channel. The signal channel amplifies the biological signal to generate a detection current and includes a capacitive-coupled transconductance amplifier. The capacitive-coupled transconductance amplifier amplifies the biological signal with a transconductance gain to generate a first current.

Systems and methods for amplifying signals. In some embodiments, the signals may be amplified using a diode steering network with an amplifier operated in class AB mode. In some embodiments, distortion in the amplified signal may be corrected using a feed forward cancellation circuit operated in class A mode.

Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.

Methods and systems for accurate gain adjustment of a transimpedance amplifier using a dual replica and servo loop is disclosed and may include, in a transimpedance amplifier (TIA) circuit comprising a first TIA, a second TIA, and a third TIA, each comprising a configurable feedback impedance, and a control loop, where the control loop comprises a gain stage with inputs coupled to outputs of the first and second TIAs and an output coupled to the configurable feedback impedance of the second and third TIAs: configuring a gain level of the first TIA by configuring its feedback impedance, configuring a gain level of the third TIA by configuring a reference current applied to an input of the first TIA, and amplifying a received electrical signal to generate an output voltage utilizing the third TIA. The reference current may generate a reference voltage at one of the inputs of the gain stage.

A system includes a transimpedance amplifier, disposed on a chip, having a front-end section and a back-end section; an on-chip linear regulator, on the chip, arranged to power the front-end section; and an off-chip switching regulator, off the chip, arranged to power the back-end section. The arrangement provides low noise power supply for the front-end section, while providing a more power efficient switching regulator to power the back-end section. The output voltage of the on-chip linear regulator and the output voltage of the off-chip switching regulator are controlled to be the same.

An amplification device includes a base substrate, an amplification element, and a matching circuit board. The amplification element is mounted on the base substrate. The matching circuit board is mounted on the base substrate and includes a circuit pattern which is electrically connected to the amplification element. The matching circuit board includes a first side surface and a second side surface each extending in the longitudinal direction of the matching circuit board. A first recess is provided in the first side surface. A second recess facing the first recess is provided in the second side surface.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.

An apparatus includes: a transistor including an input terminal for an input signal and an output terminal for an output signal; a matching circuit configured to match a load impedance regarding a fundamental harmonic of at least one of the input signal and the output signal to an impedance of the transistor and include a first conductive film being laminated over the transistor and coupled to at least one of the input terminal and the output terminal; and a processing circuit configured to adjust an impedance regarding a harmonic of at least one of the input signal and the output signal and include a second conductive film being laminated over the first conductive film and coupled to at least one of the input terminal and the output terminal through a via which penetrates through a dielectric layer sandwiched between the first conductive film and the second conductive film.