A compensation circuit includes a power amplifier, a current bias circuit, a power detection circuit and a current control circuit; the power detection circuit is configured to detect the voltage amplitude of the radio frequency input signal of the power amplifier and output a reference current when the voltage amplitude meets a preset condition; the current control circuit is configured to receive a reference current and output a compensation current to the current bias circuit based on the reference current; the current bias circuit is configured to receive the compensation current and generate the direct-current bias current, and output the compensation current and the direct-current bias current to the power amplifier; and the power amplifier is configured to receive the compensation current and the direct-current bias current, and amplify the power of the radio frequency input signal based on the compensation current and the direct-current bias current.

The present application provides a data acquisition method, a data acquisition apparatus, a data acquisition device and a storage medium. The data acquisition method includes: obtaining a first storage flag for indicating a flag bit at which first data starts to be acquired and stored; when a first data acquisition clock is asynchronous with a second data acquisition clock, obtaining a second storage flag being a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition cock to the second data acquisition clock, according to the first data acquisition clock and the second data acquisition clock; and performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, a delay between the first data and the second data acquired each time is kept unchanged.

The present application provides a data acquisition method, a data acquisition apparatus, a data acquisition device and a storage medium. The data acquisition method includes: obtaining a first storage flag for indicating a flag bit at which first data starts to be acquired and stored; when a first data acquisition clock is asynchronous with a second data acquisition clock, obtaining a second storage flag being a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition cock to the second data acquisition clock, according to the first data acquisition clock and the second data acquisition clock; and performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, a delay between the first data and the second data acquired each time is kept unchanged.

The present disclosure relates to a transmitter system that includes a radio frequency (RF) power amplifier (PA) and a baseband processor. The RF PA is configured to amplify an RF input signal to an RF output signal and configured to receive an analog bias adjustment signal, which is applied to correct dynamic bias errors in the RF PA caused by amplification variations that have time constants. The baseband processor, in response to an input envelope and a feedback output envelope, is configured to generate a feedback envelope error signal. Herein, the input envelope is estimated based on a baseband input signal received by the baseband processor, and the feedback output envelope is estimated based on the RF output signal. The RF input signal and the analog bias adjustment signal fed to the RF PA are generated from the baseband input signal and the feedback envelope error signal, respectively.

Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.

Circuit techniques for providing base-current cancellation of a bipolar junction transistor (BJT) differential pair that compensate for tail current noise and differential voltage transients without penalizing supply headroom.

In an embodiment, an electronic circuit includes: an input differential pair including first and second transistors; a first pair of transistors in emitter-follower configuration including third and fourth transistors, and an output differential pair including fifth and sixth transistors. The third transistor has a control terminal coupled to the first transistor, and a current path coupled to a first output terminal. The fourth transistor has a control terminal coupled to the second transistor, and a current path coupled to a second output terminal. The fifth transistor has a control terminal coupled to the first transistor, and a first current path terminal coupled to the first output terminal. The sixth transistor has a control terminal coupled to the second transistor, and a first current path terminal coupled to the second output terminal. First and second termination resistors are coupled between the first pair of transistors and the output differential pair.

A transceiver is configured for a calibration mode of operation in which an impedance of a transmit chain is tuned responsive to a power measurement of a mixed RF calibration signal to form a tuned transmit chain. A direct conversion mixes an RF calibration signal with a DC offset signal to form the mixed calibration signal. During a normal mode of operation, a heterodyne mixer mixes an LO signal with an IF signal to produce an RF signal that is amplified through the tuned transmit chain.

A transmitter for a communication system comprises a digital pre-distortion (DPD) circuit and adaptation circuitry. The DPD circuit is configured to generate a digital intermediate signal by compensating an input signal for distortions resulting from an amplifier. The amplifier is configured to output an output signal based on the digital intermediate signal. The DPD circuit includes one or more an infinite impulse response (IIR) filters configured to implement a first transfer function based on a first parameter, and a second transfer function based on the first parameter and a time constant. The DPD circuit is configured to generate an adjustment signal based on the first transfer function and the second transfer function. The adaptation circuitry is configured to update the first parameter based on the adjustment signal, the input signal, and the output signal.