Programmable clamping methods and devices providing adjustable clamping powers to accommodate different applications and requirements are disclosed. The described devices can use switchable clamping circuits having different structures, body-controlled clamping circuits, or clamping circuits adjusting their input power levels using programmable resistive ladders. Examples of how the disclosed devices can be combined to improve design flexibility are also provided.

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

An integrated circuit may include one or more circuits coupled to capacitance multiplier circuitry. The capacitance multiplier circuitry may include a capacitor, fixed and tunable resistances, and a transconductance circuit. The tunable resistance can be adjusted to control the overall capacitance of the capacitance multiplier circuitry. The transconductance circuit may include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component may be a diode-connected transistor, a direct shorting wire, a resistor, an inductor, or a current source. The second electrical component may be a current source, a direct shorting wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuitry can provide a large adjustable amount of capacitance without a voltage drop and without consuming a large amount of power.

An integrated circuit may include one or more circuits coupled to capacitance multiplier circuitry. The capacitance multiplier circuitry may include a capacitor, fixed and tunable resistances, and a transconductance circuit. The tunable resistance can be adjusted to control the overall capacitance of the capacitance multiplier circuitry. The transconductance circuit may include a transistor having a drain terminal coupled to a first electrical component and a source terminal coupled to a second electrical component. The first electrical component may be a diode-connected transistor, a direct shorting wire, a resistor, an inductor, or a current source. The second electrical component may be a current source, a direct shorting wire, a resistor, an inductor, or another diode-connected device. Configured in this way, the capacitance multiplier circuitry can provide a large adjustable amount of capacitance without a voltage drop and without consuming a large amount of power.

A low noise amplifier includes a first input port configured to receive a first input signal, a second input port configured to receive a second input signal, and a first amplifier stage including a first gain stage connected to the first input port and the second input port, and a first drive stage between the first gain stage and a first load circuit. The first gain stage includes a first-first gain block connected to the first input port, a first-second gain block connected to the second input port, and a first degeneration inductor between a ground terminal and a first common node of the first-first gain block and the first-second gain block. The amplifier includes a second amplifier stage including a second gain stage connected to the first input port and the second input port, and a second drive stage between the second gain stage and a second load.

A fast-switching average power tracking (APT) power management integrated circuit (PMIC) is provided. The fast-switching APT PMIC includes a voltage amplifier(s) and an offset capacitor(s) having a small capacitance (e.g., between 10 nF and 200 nF). The voltage amplifier(s) is configured to generate an initial APT voltage(s) based on an APT target voltage(s) and the offset capacitor(s) is configured to raise the initial APT voltage(s) by an offset voltage(s) to generate an APT voltage(s). In embodiments disclosed herein, the offset voltage(s) is modulated based on the APT target voltage(s). Given the small capacitance of the offset capacitor(s), it is possible to adapt the offset voltage(s) fast enough to thereby change the APT voltage(s) within a predetermined temporal limit (e.g., 0.5 μs). As a result, the fast-switch APT PMIC can enable a power amplifier(s) to support dynamic power control with improved linearity and efficiency.

A fast-switching average power tracking (APT) power management integrated circuit (PMIC) is provided. The fast-switching APT PMIC includes a voltage amplifier(s) and an offset capacitor(s) having a small capacitance (e.g., between 10 nF and 200 nF). The voltage amplifier(s) is configured to generate an initial APT voltage(s) based on an APT target voltage(s) and the offset capacitor(s) is configured to raise the initial APT voltage(s) by an offset voltage(s) to generate an APT voltage(s). In embodiments disclosed herein, the offset voltage(s) is modulated based on the APT target voltage(s). Given the small capacitance of the offset capacitor(s), it is possible to adapt the offset voltage(s) fast enough to thereby change the APT voltage(s) within a predetermined temporal limit (e.g., 0.5 μs). As a result, the fast-switch APT PMIC can enable a power amplifier(s) to support dynamic power control with improved linearity and efficiency.

Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.

Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.

Optical amplification apparatus (1) for a submarine optical amplifier (90), the optical amplification apparatus (1) comprising an optical amplification system (2), comprising at least one active component (3), and a DC/DC converter (4) connected to supply the optical amplification system (2), wherein the DC/DC converter (4) comprises a first commutator (5) and a pulse modulator (6) connected to the first commutator (5) for cyclically switching with a duty cycle the first commutator (5) between a closing configuration, in which it can be passed thought by a current, and an opening configuration, in which it cannot be passed thought by the current, characterized in that the DC/DC converter (4) comprises a retroaction circuit (7) comprising, a first differential amplifier (8) connected for receiving, at a first input port, a first signal (100) representative of at least a voltage at output from the DC/DC converter (4) and at input into the optical amplification system (2) and, at a second input port, a first reference signal (201), the first differential amplifier (8) being structured for generating a first error signal (101) representative of a difference between the first signal (100) and the first reference signal (201), a second differential amplifier (9) connected to the first differential amplifier (8) for receiving, at a first respective input port, the first error signal (101) and, at a second respective input port, a second reference signal (201), the second differential amplifier (9) being structured for generating a second error signal (102) representative of a difference between the first error signal (101) and the second reference signal (201), wherein the second error signal (102) is proportional to a deviation of the voltage at output from the DC/DC converter (4) with respect to a nominal working voltage of the optical amplification system (2), in that the first input port of the first differential amplifier (8) and the first respective input port of the second differential amplifier (9) are concordant ports, and in that the pulse modulator (6) is connected to the second differential amplifier (9) for receiving the second error signal (102) and for regulating the duty cycle as a function of the second error signal (102).