H03F3/005

Device and method for enhancing voltage regulation performance

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

Analog neural memory array storing synapsis weights in differential cell pairs in artificial neural network

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W− values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)−(W−). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W− values.

VOICE ACTIVITY DETECTION SYSTEM AND ACOUSTIC FEATURE EXTRACTION CIRCUIT THEREOF
20230067657 · 2023-03-02 ·

An acoustic feature extraction (AFE) circuit includes a plurality of band-pass filters (BPFs) adaptable to a plurality of channels with different band-pass frequency ranges respectively for switchably receiving an amplified signal, thereby generating corresponding filtered signals, the plurality of BPFs including an operational amplifier that is shared among the plurality of channels; and a rectifier switchably coupled to receive the filtered signals, thereby generating a rectified signal. The amplified signal is time-division demultiplexed onto the BPFs in different phases, and the filtered signals are time-division multiplexed onto the rectifier in different phases.

ELECTRONIC DEVICE INCLUDING A PLURALITY OF POWER AMPLIFIERS AND OPERATING METHOD THEREOF
20220329221 · 2022-10-13 ·

Various embodiments of the disclosure relate to a device and a method for supplying power to a plurality of power amplifiers in an electronic device. An electronic device may include: a first power amplifier, a second power amplifier, a third power amplifier, a first power supply module including a power supply configured to supply power to the first power amplifier or the second power amplifier, a second power supply module including a power supply configured to supply power to the second power amplifier or the third power amplifier, and a detection module comprising circuitry configured to identify a state of a connection between the second power amplifier and the first power supply module and a state of a connection between the second power amplifier and the second power supply module, wherein the detection module may be configured to output a power control signal based on detecting that the second power amplifier is connected to the first power supply module and the second power supply module, wherein power supply to the second power amplifier from the first power supply module or the second power supply module may be shut off based on the power control signal of the detection module.

Techniques for determining energy storage device state of health

Techniques for determining a state of health of an energy storage device that utilize a capacitor gain amplifier to provide an AC gain and block the DC voltage. An input capacitor can couple between an input excitation signal generator circuit and the amplifier's inverting input terminal, and a feedback capacitor can couple between the amplifier's inverting input terminal and the amplifier's output. A switch can be used to reset the feedback capacitor periodically to prevent the amplifier's output from becoming saturated from a leakage current at the inverting input terminal of the amplifier.

Methods and Devices for Ramping a Switched Capacitor Power Amplifier
20170373649 · 2017-12-28 · ·

A method for ramping a switched capacitor power amplifier is disclosed, where the switched capacitor power amplifier comprises a plurality of capacitors in a capacitor bank, and where a number of the capacitors in the capacitor bank are activated. The method comprises changing the number of capacitors in the capacitor bank that are activated, maintaining the changed number of activated capacitors in the capacitor bank for a period of time, and repeating the changing and maintaining, where a length of the period of time is varied between at least two repetitions of the maintaining.

CONVERSION CIRCUIT AND DETECTION CIRCUIT

A conversion circuit for converting a current signal into a first output voltage signal, where the current signal flows through a sensing component, is provided. The conversion circuit includes: a first current eliminating circuit, configured to eliminate a first current in the current signal. The first current eliminating circuit includes: a current sample and hold circuit; and a current driving circuit, coupled between the sensing component and the current sample and hold circuit; a second current eliminating circuit, coupled to the sensing component and configured to eliminate a second current in the current signal; and an integrating circuit, coupled to the sensing component and configured to integrate a third current in the current signal, and output a first input voltage signal between a first integration output terminal and a second integration output terminal.

Integrating Circuit and Capacitance Sensing Circuit
20170364180 · 2017-12-21 ·

The present disclosure is applied to touch technology, and provides an integrating circuit. The integrating circuit comprises an impedance unit, an amplifier, an integration capacitor, a discharge capacitor, a first switch and a second switch. The amplifier comprises a first input terminal, a second input terminal and an output terminal configured to output an output signal; the integration capacitor is coupled between the first input terminal and the output terminal; the first switch is coupled between the first input terminal of the amplifier and the second terminal of the discharge capacitor; and the second switch is coupled between the first terminal and the second terminal of the discharge capacitor.

SWITCHED INDUCTOR/TRANSFORMER FOR DUAL-BAND LOW-NOISE AMPLIFIER (LNA)
20170366146 · 2017-12-21 ·

Certain aspects of the present disclosure generally relate to an amplifier configured to process signals received in different frequency bands, where at least a portion of the amplifier is shared between different modes corresponding to the different frequency bands. One example circuit generally includes an amplifier having at least one first transistor configured to amplify a first signal received in a first mode of operation (e.g., associated with a particular frequency band), and at least one second transistor configured to amplify a second signal received in a second mode of operation. The amplifier may also include a transformer comprising a primary winding and a secondary winding, and one or more switches configured to selectively couple the primary winding to the first transistor or the second transistor based on the first mode or the second mode of operation, respectively. In certain aspects, the transformer may be coupled to a transconductance circuit.

HARMONIC TRAPPING TECHNIQUES FOR TRANSMITTER INTERSTAGE MATCHING

A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.