A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS), includes a pixel circuit, a VSL circuit, and an amplifier. The pixel circuit may generate a reset voltage and a signal voltage, based on a power supply connected to the pixel circuit and/or intensity of light captured by the pixel circuit. The VSL circuit may store pixel information in a pixel load based on settling a voltage at the pixel load to the signal voltage and/or set the voltage at the pixel load to a pixel reset voltage based on settling the voltage at the pixel load to the reset voltage. The amplifier may generate a voltage, based on varying a resistance at an input of the amplifier, to enable the VSL circuit to store the pixel information and/or set the voltage at the pixel load to the pixel reset voltage.

A circuit which reuses current to synthesize a negative impedance includes a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit is arranged to provide at least one predetermined current, wherein the current source circuit has a first connection port and a second connection port, and the first connection port of the current source is coupled to a first reference voltage. The differential circuit is coupled between the second connection port of the current source circuit and a second reference voltage, and is arranged to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port. The negative impedance conversion circuit is coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.

A circuit which reuses current to synthesize a negative impedance includes a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit is arranged to provide at least one predetermined current, wherein the current source circuit has a first connection port and a second connection port, and the first connection port of the current source is coupled to a first reference voltage. The differential circuit is coupled between the second connection port of the current source circuit and a second reference voltage, and is arranged to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port. The negative impedance conversion circuit is coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.

An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.

An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.

An envelope tracking (ET) integrated circuit (ETIC) supporting multiple types of power amplifiers. The ETIC includes a pair of tracker circuits configured to generate a pair of low-frequency currents at a pair of output nodes, respectively. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages at the output nodes, respectively. In various embodiments disclosed herein, the ETIC can be configured to generate the low-frequency currents independent of what type of power amplifier is coupled to the output nodes. Concurrently, the ETIC can also generate the ET voltages in accordance with the type of power amplifier coupled to the output nodes. As such, it is possible to support multiple types of power amplifiers based on a single ETIC, thus helping to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ETIC and the multiple types of power amplifiers.

A harmonic processing circuit includes a first inductor having a first end connected to a connection line connected between an amplifier and an impedance matching circuit, and a second end connected to a first node, a first transmission line having a third end connected to the first node and a fourth end connected to a second node, and a parallel resonant circuit having a fifth end connected to the second node and a sixth end connected to a reference potential, wherein a second inductor and a first capacitor are connected in parallel between the fifth end and the sixth end, wherein when the first inductor is viewed from the connection line, an impedance at a frequency of a fundamental wave amplified by the amplifier is larger than an impedance at a frequency of a second harmonic having twice the frequency of the fundamental wave.

A harmonic processing circuit includes a first inductor having a first end connected to a connection line connected between an amplifier and an impedance matching circuit, and a second end connected to a first node, a first transmission line having a third end connected to the first node and a fourth end connected to a second node, and a parallel resonant circuit having a fifth end connected to the second node and a sixth end connected to a reference potential, wherein a second inductor and a first capacitor are connected in parallel between the fifth end and the sixth end, wherein when the first inductor is viewed from the connection line, an impedance at a frequency of a fundamental wave amplified by the amplifier is larger than an impedance at a frequency of a second harmonic having twice the frequency of the fundamental wave.

A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.

A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.