A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output, and a feedback path that couples the signal output to the signal input, wherein the feedback path includes an anti-parallel circuit of diodes, and a voltage divider including a first and a second divider resistor and a voltage divider tap between the first and the second divider resistor, wherein the voltage divider couples the signal output to a reference potential terminal, and the voltage divider tap is coupled to the anti-parallel circuit of diodes and the anti-parallel circuit of diodes is coupled to the signal input.

A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output, and a feedback path that couples the signal output to the signal input, wherein the feedback path includes an anti-parallel circuit of diodes, and a voltage divider including a first and a second divider resistor and a voltage divider tap between the first and the second divider resistor, wherein the voltage divider couples the signal output to a reference potential terminal, and the voltage divider tap is coupled to the anti-parallel circuit of diodes and the anti-parallel circuit of diodes is coupled to the signal input.

A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

A circuit having an input and an output, the circuit comprising: a first amplifier having a first input, a second input and an output coupled to the output of the circuit; a first capacitor having a first terminal coupled to the first input of the first amplifier and a second terminal coupled to the output of the first amplifier; a first resistor having a first terminal coupled to the first input of the first amplifier and a second terminal; a buffer having an output coupled to the second terminal of the first resistor and an input; a second resistor having a first terminal coupled to the output of the first amplifier and a second terminal coupled to the input of the buffer; a second capacitor coupled between the input of the buffer and ground; and a third resistor coupled between the input of the buffer and the input of the circuit.

A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS), includes a pixel circuit, a VSL circuit, and an amplifier. The pixel circuit may generate a reset voltage and a signal voltage, based on a power supply connected to the pixel circuit and/or intensity of light captured by the pixel circuit. The VSL circuit may store pixel information in a pixel load based on settling a voltage at the pixel load to the signal voltage and/or set the voltage at the pixel load to a pixel reset voltage based on settling the voltage at the pixel load to the reset voltage. The amplifier may generate a voltage, based on varying a resistance at an input of the amplifier, to enable the VSL circuit to store the pixel information and/or set the voltage at the pixel load to the pixel reset voltage.

A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS), includes a pixel circuit, a VSL circuit, and an amplifier. The pixel circuit may generate a reset voltage and a signal voltage, based on a power supply connected to the pixel circuit and/or intensity of light captured by the pixel circuit. The VSL circuit may store pixel information in a pixel load based on settling a voltage at the pixel load to the signal voltage and/or set the voltage at the pixel load to a pixel reset voltage based on settling the voltage at the pixel load to the reset voltage. The amplifier may generate a voltage, based on varying a resistance at an input of the amplifier, to enable the VSL circuit to store the pixel information and/or set the voltage at the pixel load to the pixel reset voltage.

An amplifier circuit with an overshoot suppress scheme is provided. The amplifier circuit includes an input amplifier, an output amplifier and a diode device. The output amplifier is coupled to the input amplifier and outputs an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

An envelope tracking (ET) power management apparatus incorporating multiple power amplifiers is provided. The ET power management apparatus includes a single ET integrated circuit (ETIC) configured to provide multiple ET voltages to the multiple power amplifiers for amplifying a radio frequency (RF) signal concurrently. The ETIC includes multiple first ET voltage circuits configured to generate multiple first ET voltages and a second ET voltage circuit configured to generate a second ET voltage. The ETIC is configured to provide each of the first ET voltages to an output stage amplifier(s) in a respective one of the power amplifiers and provide the second ET voltage to a driver stage amplifier in all of the power amplifiers. By supporting the multiple power amplifiers using a single ETIC, it is possible to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ET power management apparatus.

A circuit which reuses current to synthesize a negative impedance includes a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit is arranged to provide at least one predetermined current, wherein the current source circuit has a first connection port and a second connection port, and the first connection port of the current source is coupled to a first reference voltage. The differential circuit is coupled between the second connection port of the current source circuit and a second reference voltage, and is arranged to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port. The negative impedance conversion circuit is coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.

A circuit which reuses current to synthesize a negative impedance includes a current source circuit, a differential circuit, and a negative impedance conversion circuit. The current source circuit is arranged to provide at least one predetermined current, wherein the current source circuit has a first connection port and a second connection port, and the first connection port of the current source is coupled to a first reference voltage. The differential circuit is coupled between the second connection port of the current source circuit and a second reference voltage, and is arranged to receive a differential input pair and generate a differential output pair, wherein the differential circuit has a differential output port. The negative impedance conversion circuit is coupled between the differential output port and a third reference voltage, wherein the third reference voltage is different from the first reference voltage.