Implementations disclosed describe an integrated circuit (IC) having a plurality of reconfigurable analog circuits that include a finite state machine (FSM) logic circuit and further include an interface to receive an input signal. In a first IC configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the IC may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the FSM logic circuit processing the first output value, the IC may reconfigure the plurality of reconfigurable analog circuits into a second IC configuration having a second configuration setting.

A multiphase power supply includes a multiphase converter including first and second converters having differing operating phases, each of the first and second converters configured to convert input power into driving power, and transmit the driving power to a power amplifier, a detector configured to detect a voltage based on the driving power, and a duty controller configured to compare an error voltage between an envelope signal of an input signal input into the power amplifier and the detected voltage and sawtooth wave signals having different phases from each other to generate duty control signals, wherein the duty controller compares the error voltage and the sawtooth wave signals with each other using a single comparator.

A multiphase power supply includes a multiphase converter including first and second converters having differing operating phases, each of the first and second converters configured to convert input power into driving power, and transmit the driving power to a power amplifier, a detector configured to detect a voltage based on the driving power, and a duty controller configured to compare an error voltage between an envelope signal of an input signal input into the power amplifier and the detected voltage and sawtooth wave signals having different phases from each other to generate duty control signals, wherein the duty controller compares the error voltage and the sawtooth wave signals with each other using a single comparator.

A high-frequency module includes a module substrate having main surfaces, one or more module components disposed on the main surface, a resin member covering the main surface, and a metal shield layer covering a top surface of each of the resin member and the one or more module components, and set to ground potential. A sub-module component, which is one of the one or more module components, has a sub-module substrate having main surfaces, a first circuit component disposed on the main surface, one or more second circuit components disposed on the main surface, a resin member covering the main surface, and a side surface shield layer covering a side surface of each of the resin member and the sub-module substrate, and set to the ground potential. An end surface on a top surface side of the side surface shield layer contacts the metal shield layer.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

An eVC including coarse and fine tuning networks. The coarse tuning network includes a circuit: receiving a RF input signal from a RF generator; outputting a RF output signal to a reference terminal or load; and receiving a DC bias voltage. The circuit is switched between first and second states. A capacitance of the circuit is based on the DC bias voltage while in the first state and is not based on the DC bias voltage while in the second state. The fine tuning network is connected in parallel with the coarse tuning network and includes a varactor. The varactor includes: a first diode receiving the RF input signal; and a second diode connected in a back-to-back configuration with the first diode and outputting a RF output signal to the reference terminal or load. A capacitance of the varactor is based on a second received DC bias voltage.

An envelope tracking (ET) power management apparatus incorporating multiple power amplifiers is provided. The ET power management apparatus includes a single ET integrated circuit (ETIC) configured to provide multiple ET voltages to the multiple power amplifiers for amplifying a radio frequency (RF) signal concurrently. The ETIC includes multiple first ET voltage circuits configured to generate multiple first ET voltages and a second ET voltage circuit configured to generate a second ET voltage. The ETIC is configured to provide each of the first ET voltages to an output stage amplifier(s) in a respective one of the power amplifiers and provide the second ET voltage to a driver stage amplifier in all of the power amplifiers. By supporting the multiple power amplifiers using a single ETIC, it is possible to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ET power management apparatus.

An envelope tracking (ET) power management apparatus incorporating multiple power amplifiers is provided. The ET power management apparatus includes a single ET integrated circuit (ETIC) configured to provide multiple ET voltages to the multiple power amplifiers for amplifying a radio frequency (RF) signal concurrently. The ETIC includes multiple first ET voltage circuits configured to generate multiple first ET voltages and a second ET voltage circuit configured to generate a second ET voltage. The ETIC is configured to provide each of the first ET voltages to an output stage amplifier(s) in a respective one of the power amplifiers and provide the second ET voltage to a driver stage amplifier in all of the power amplifiers. By supporting the multiple power amplifiers using a single ETIC, it is possible to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ET power management apparatus.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.