Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.

Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.

A current replication circuit includes a bias circuit and a first transistor sized, relative to a second transistor to be sensed, according to a first scaling factor, the first transistor having an on-resistance associated therewith. The current replication circuit further includes at least one transconductance amplifier having first and second signal paths. The first signal path is connected with the bias circuit in a closed loop configuration such that a quiescent bias point of the transconductance amplifier is controlled as a function of the on-resistance of the first transistor. The second signal path is connected with the second transistor in an open loop configuration and is adapted to convert a sensed input voltage to a corresponding current output signal as a function of the quiescent bias point of the transconductance amplifier, the current output signal being proportional to a current flowing through the second transistor.

An amplifier system including a push-pull power amplifier having an input to receive a radio frequency (RF) input signal and an output, the push-pull power amplifier being configured to amplify the RF input signal and provide at the output an RF output signal that is an amplified version of the RF input signal, a switchable shunt capacitance switchably connected between a load-line connected to the output of the push-pull power amplifier and a reference potential, and a switch configured to selectively connect the switchable shunt capacitance to the reference potential and disconnect the switchable shunt capacitance from the reference potential to vary an impedance of load-line.

An amplifier system including a push-pull power amplifier having an input to receive a radio frequency (RF) input signal and an output, the push-pull power amplifier being configured to amplify the RF input signal and provide at the output an RF output signal that is an amplified version of the RF input signal, a switchable shunt capacitance switchably connected between a load-line connected to the output of the push-pull power amplifier and a reference potential, and a switch configured to selectively connect the switchable shunt capacitance to the reference potential and disconnect the switchable shunt capacitance from the reference potential to vary an impedance of load-line.

Certain aspects of the present disclosure provide amplifiers. Certain aspects of the present disclosure provide methods and apparatus for protecting an such amplifiers, for example an audio amplifier, or a delta-sigma modulator from saturation. One example amplifier generally includes an output stage comprising a plurality of transistors; and a feedback network having an input coupled to an output of the output stage and comprising a plurality of integrators connected in series. At least one of the plurality of integrators generally includes an operational amplifier having an input and an output, a first resistive element coupled to the input of the operational amplifier, a capacitive element coupled between the input and the output of the operational amplifier; and a first switch coupled between the input and the output of the operational amplifier. For certain aspects, the amplifier may be a class-D amplifier or a direct digital feedback amplifier (DDFA).

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

An input driver includes a power converting unit and a level adjusting unit. The power converting unit is configured to generate a first power and a second power having an anti-phase relationship based on input power, and process the first power and the second power as differential inputs to output a third power. The level adjusting unit is configured to adjust a voltage level of the third power and output the adjusted power as an input to a power amplifier.

An input driver includes a power converting unit and a level adjusting unit. The power converting unit is configured to generate a first power and a second power having an anti-phase relationship based on input power, and process the first power and the second power as differential inputs to output a third power. The level adjusting unit is configured to adjust a voltage level of the third power and output the adjusted power as an input to a power amplifier.

An ultrasound probe buffer is provided. The ultrasound probe buffer may include a high impedance amplifier having a common-source core stage with series-series local feedback. The high impedance amplifier may include a first MOSFET and a second MOSFET, wherein a source terminal of the first MOSFET is coupled to a source terminal of the second MOSFET.