Systems and methods for amplifying signals. In some embodiments, the signals may be amplified using a diode steering network with an amplifier operated in class AB mode. In some embodiments, distortion in the amplified signal may be corrected using a feed forward cancellation circuit operated in class A mode.

Systems and methods for amplifying signals. In some embodiments, the signals may be amplified using a diode steering network with an amplifier operated in class AB mode. In some embodiments, distortion in the amplified signal may be corrected using a feed forward cancellation circuit operated in class A mode.

A circuit includes a reference voltage circuit, a filter circuit configured to receive an output of the reference voltage circuit, and a voltage follower configured to receive an output of the filter circuit and generate a bias voltage. The filter circuit is configured to combine signals on a reference ground with the output of the reference voltage circuit. A method of providing a bias voltage includes generating a reference voltage using a reference voltage circuit, filtering the reference voltage to generate a second voltage using a filter circuit, and generating the bias voltage according to the second voltage using a voltage follower circuit. Filtering the reference voltage includes combining a fluctuation of the reference ground with the reference voltage.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.

A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

There are disclosed various methods and apparatuses. In some embodiments of the method an input signal is provided to an input of a first transistor of a push-pull circuit via a first slew-rate adjuster; and the input signal is also provided to an input of a second transistor of the push-pull circuit via a second slew-rate adjuster. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster to switch the first transistor on after the second transistor switches off when the amplitude of the input signal increases. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster the input signal to switch the second transistor on after the first transistor switches off when the amplitude of the input signal decreases. In some embodiments the apparatus comprises a push-pull circuit comprising a first transistor and a second transistor; an input to receive an input signal; a first slew-rate adjuster adapted to provide the input signal to the input of the first transistor; and a second slew-rate adjuster adapted to provide the input signal to the input of the second transistor. A time constant of the first slew-rate adjuster is dependent on the direction of change of the input signal, and a time constant of the second slew-rate adjuster is dependent on the direction of change of the input signal.

Various implementations include systems for amplifying input signals. In particular implementations, a system includes a common mode voltage controller configured to receive an input signal and output a pair of adjusted signals; a modulator that generates a pair of pulse width modulation (PWM) signals in response to the adjusted signals; and a self-boosting push pull amplifier configured to receive the PWM signals and generate an amplified output, wherein the self-boosting push pull amplifier is configured to generate a differential mode voltage representative of an amplified version of the input signal, wherein the adjusted audio signals generated by the common mode voltage controller include a dynamically adjusted gain and duty cycle offset that causes the self-boosting push pull amplifier to operate with a reduced common mode voltage.

A power amplifier circuit includes a first amplifier; a first transformer including a first primary coil connected to an output of the first amplifier and a first secondary coil electromagnetically coupled to the first primary coil; a second amplifier connected to one end of the first secondary coil; a third amplifier connected to another end of the first secondary coil; a second transformer including a second primary coil having one end connected to an output of the second amplifier and another end connected to an output of the third amplifier, and a second secondary coil electromagnetically coupled to the second primary coil; a first capacitance element provided between the second secondary coil and a ground; and a second capacitance element having one end connected to one end of the second secondary coil and another end connected to another end of the second secondary coil.

A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

An auto-tuning controller for improving a performance of a power amplifier system is provided. The controller includes an interface including input terminals and output terminals, the interface being configured to acquire input signal conditions of power amplifiers (PAs), a training circuit including a processor and a memory running and storing a Digital Doherty amplifier (DDA) controller (module), a DPD controller (module) and a DDA-DPD neural network (NN). The training circuit is configured to perform sampling the input signal conditions, and selecting a DPD model from a set of polynomial models for the DPD controller and a set of DDA optimization variables for the DDA controller, using optimized DPD model and DDA coefficients, wherein the optimized DPD model and DDA coefficients are provided by performing an offline optimization for the DPD model and DDA coefficients based on a predetermined optimization method, collecting the optimized DPD coefficients and optimized DDA optimization variables, generating online-DDA optimal coefficients and DPD optimal coefficients using a trained DDA-DPD NN, and updating the generated optimal DDA and DPD coefficients via the output terminals of the interface.