An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.

A driver circuit is provided. The driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is configured to be coupled to switch a first input stage circuit to one of a first output stage circuit and a second output stage circuit, and the at least one power switching circuit is further coupled to switch a second input stage circuit to the other one of the first output stage circuit and the second output stage circuit.

A receiver signal path includes a high pass filter that centers a received differential pair of signals around a common mode voltage to generate a centered received differential pair of signals. The receiver signal path includes a demodulator that removes a carrier signal from the centered received differential pair of signals to generate a demodulated signal and generates a logic signal based on the demodulated signal and a predetermined threshold signal. The demodulator includes a differential stage including an extremum selector circuit that generates the demodulated signal based on the centered received differential pair of signals. The demodulated signal corresponds to a mean level of the rectified version of the centered received differential pair of signals. The differential stage includes a second circuit that provides the reference signal based on the predetermined threshold signal. The logic signal is based on a comparison of the demodulated signal to the reference signal.

An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

A communication system including an analog front end and an automatic gain controller. The analog front end includes at least one amplifier for amplifying a received analog signal and an analog to digital converter that converts the analog signal to digital samples. The automatic gain controller includes comparator circuitry, counter circuitry, and a gain controller. The comparator circuitry compares each of the digital samples with an upper threshold and a lower threshold. The counter circuitry counts a high count number of the digital samples having magnitudes that are greater than the upper threshold during each count window and counts a low count number of the digital samples having magnitudes that are less than the lower threshold during the count window. The gain controller adjusts a gain of the at least one amplifier by an amount based on the high count number and the low count number.

Apparatus useful for receiving or transmitting voltage signals might include a current generator having first and second inputs and configured to generate a current flow between first and second outputs responsive to a voltage difference between its first and second inputs. The apparatus might further include a feedback amplifier having a first input connected to the first output of the current generator, a second input connected to the second output of the current generator, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.

An apparatus can include tracking circuitry coupled to a current source and configured to generate a reference voltage signal based on a reference current signal from the current source. The apparatus can include voltage regulator circuitry coupled to the tracking circuitry and configured to generate a voltage supply signal based on the reference voltage signal. The apparatus can further include amplifier circuitry configured to amplify an input signal based on the voltage supply signal. The reference voltage signal can track process and temperature variations associated with at least one field effect transistor within the tracking circuitry. The voltage regulator circuitry can be configured to operate with a closed loop gain higher than 1. The tracking circuitry includes a first transistor connected in parallel with a second transistor, the first and second transistors having a complimentary type with each other (e.g., NMOS and PMOS transistors).

Disclosed herein are circuits, devices and methods that address challenges associated with power amplifier systems. A power amplifier system includes two or more fast error amplifiers coupled to corresponding power amplifiers. The fast error amplifiers are configured to generate envelope tracking signals based on a signal envelope, the envelope tracking signals modifying a DC-DC regulated voltage from a DC-DC converter to more efficiently operate the power amplifiers. By splitting the envelope tracking between two or more fast error amplifiers and amplification between corresponding two or more power amplifiers, the power, frequency or bandwidth, linearity, signal-to-noise ratio, efficiency, or the like of the power amplifier system can be improved. Wireless communications configurations with such power amplifier systems can provide uplink carrier aggregation and/or cellular signals based on standards and protocols that require increased bandwidth and/or power.

A circuit includes a Superconducting Quantum Interference Array (SQIF), a bias circuit, and a coil. The SQIF generates an output voltage that is a transfer function of the magnetic flux perpendicularly passing through the SQIF. An external magnetic field and a bias magnetic field supply the magnetic flux. The bias circuit generates a bias current for biasing the SQIF at an operating point. The coil generates the bias magnetic field through the SQIF from the bias current of the bias circuit. The bias magnetic field provides nullifying feedback to the SQIF that counterbalances a low-frequency portion of the external magnetic field, such that the output voltage of the SQIF detects a high-frequency portion of the external magnetic field. The circuit can be a receiver with the output voltage of the SQIF detecting an electromagnetic signal while the receiver is moving with changing orientation relative to the Earth's magnetic field.