Shoot-through condition in a component containing an amplifier with a push-pull output stage is managed. A first current in a first transistor of the output stage is mirrored to generate a first mirrored current. A second current in a second transistor of the output stage is mirrored to generate a second mirrored current. A sum of the first mirrored current and said second mirrored current is generated. When a magnitude of the sum exceeds a first pre-determined threshold, a respective control voltage of the first transistor and the second transistor is adjusted to reduce the first current and the second current at least until the sum falls below a second pre-determined threshold. In an embodiment, the first pre-determined threshold equals the second pre-determined threshold. In an embodiment, the component is a class-L power amplifier.

A wireless electric field power transmission system comprises: a transmitter comprising a transmitter antenna, the transmitter antenna comprising at least two conductors defining a volume therebetween; and at least one receiver, wherein the transmitter antenna transfers power wirelessly via electric field coupling when the at least one receiver is within the volume.

Examples of circuits, amplifiers, and stages thereof are provided that improve amplifier stability margins while maintaining signal fidelity. Example structures include pre-driver circuitry; a compensation node exhibiting high impedance during operation; a feedforward driver coupled to the pre-driver circuitry; and first and second signal mirrors; and first and second output drivers, each having a control terminal. Example structures further include feedforward circuitry in which a first node thereof is coupled to the output of the feedforward driver, a second node thereof is coupled to the control terminal of the first output driver, and a third node thereof is coupled to the control terminal of the second output driver; and compensation circuitry in which a first node thereof is coupled to the compensation node, a second node thereof is coupled to a first internal node of the first signal mirror, and a third node thereof is coupled to a second internal node of the second signal mirror.

A power-efficient neutralized signal amplifier for use in ultra-low power narrowband receiver applications. A neutralized signal amplifier having: an impedance transformation element coupled to an amplifier input and having a differential output; a gain cell, having a differential input and a differential output, the differential input coupled to the differential output of the impedance transformation element and the differential output coupled to the amplifier output; and a neutralization element coupled to the gain cell differential output and cross-coupled to the differential output of the impedance transformation element, where the coupling of the neutralization element to the differential output of the impedance transformation element provides that the input impedance of the neutralized signal amplifier is substantially determined by reflected resistive parasitics of the impedance transformation element.

In an amplifier that uses a transistor, a minimum operation voltage is lowered. An amplifier includes a P-type transistor and an N-type transistor connected in series, and an operational amplifier. An output terminal of the operational amplifier is connected to gates of both the P-type transistor and the N-type transistor. One of an inverting input terminal and a non-inverting input terminal of the operational amplifier is connected to drains of both the P-type transistor and the N-type transistor. Further, a predetermined reference voltage is applied to another of the inverting input terminal and the non-inverting input terminal.

Each sub-stage of an amplifier stage includes a resistor coupled to another resistor in an adjacent sub-stage or to a high DC voltage, the resistor and the other resistor forming part of a string of equal valued resistors; an FET having a source coupled to a cathode of a Zener diode coupled in parallel with a capacitor, a drain coupled to another sub-stage in the string, an output node of the amplifier stage, or the high DC voltage; and at least one active device coupled to a gate of the FET and coupled to the resistor for providing high impedance between a voltage on a node of the resistor and the gate of the FET and a low impedance between the at least one active device and the gate of the FET, the at least one active device coupled to both the cathode and an anode of the Zener diode.

An ultrasound circuit comprising a trans-impedance amplifier (TIA) with built-in time gain compensation functionality is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA is, in some cases, followed by further analog and digital processing circuitry.

An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier is coupled to the input amplifier and outputs an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.

A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.