An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.

There are disclosed various methods and apparatuses. In some embodiments of the method an input signal is provided to an input of a first transistor of a push-pull circuit via a first slew-rate adjuster; and the input signal is also provided to an input of a second transistor of the push-pull circuit via a second slew-rate adjuster. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster to switch the first transistor on after the second transistor switches off when the amplitude of the input signal increases. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster the input signal to switch the second transistor on after the first transistor switches off when the amplitude of the input signal decreases. In some embodiments the apparatus comprises a push-pull circuit comprising a first transistor and a second transistor; an input to receive an input signal; a first slew-rate adjuster adapted to provide the input signal to the input of the first transistor; and a second slew-rate adjuster adapted to provide the input signal to the input of the second transistor. A time constant of the first slew-rate adjuster is dependent on the direction of change of the input signal, and a time constant of the second slew-rate adjuster is dependent on the direction of change of the input signal.

There are disclosed various methods and apparatuses. In some embodiments of the method an input signal is provided to an input of a first transistor of a push-pull circuit via a first slew-rate adjuster; and the input signal is also provided to an input of a second transistor of the push-pull circuit via a second slew-rate adjuster. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster to switch the first transistor on after the second transistor switches off when the amplitude of the input signal increases. The input signal is effected by the first slew-rate adjuster and the second slew-rate adjuster the input signal to switch the second transistor on after the first transistor switches off when the amplitude of the input signal decreases. In some embodiments the apparatus comprises a push-pull circuit comprising a first transistor and a second transistor; an input to receive an input signal; a first slew-rate adjuster adapted to provide the input signal to the input of the first transistor; and a second slew-rate adjuster adapted to provide the input signal to the input of the second transistor. A time constant of the first slew-rate adjuster is dependent on the direction of change of the input signal, and a time constant of the second slew-rate adjuster is dependent on the direction of change of the input signal.

An amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, and an output node. The first capacitor is electrically connected between a first power supply node and a first node, the second capacitor is electrically connected between the first node and a second node, the third capacitor is electrically connected between a second power supply node and a third node, and the fourth capacitor is electrically connected between the third node and a fourth node. The first transistor has a gate node electrically connected to the second node, and the second transistor has a gate node electrically connected to the fourth node. The output node is selectively connected to the first transistor and the second transistor. The first node and the third node are configured to be selectively electrically connected to a voltage node and a common voltage node.

A precharge circuit comprises a gain amplifier, a comparator, a reservoir capacitor, a switch, a current source, and a switching network. The gain amplifier has a gain G1 and receives an input voltage Vrefp. The gain amplifier outputs an amplified voltage G1Vrefp to the comparator, which compares G1Vrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. The current from the current source charges the reservoir capacitor. The switching network couples the reservoir capacitor to an output of the precharge circuit during a first operating mode and provides the input voltage Vrefp to the output during a second operating mode.

A radio-frequency (RF) amplifier circuit facilites carrier-aggregation (CA) operation in a wireless communication network. A first amplifier subcircuit is coupled to an input node, and a second amplifier subcircuit is coupled to the input node. An amplifier subcircuit selector is to selectively enable operation of the first amplifier subcircuit, the second amplifier subcircuit, or the first and the second amplifier subcircuits together, in response to a selection indication. A reactive coupling network is arranged to selectively adjust the input impedance at the input node in response to the selection indication to reduce the input impedance variation.

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.

A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.