An apparatus includes a Transimpedance Amplifier (TIA), an input interface and input masking circuitry. The TIA is configured to convert input current pulses into output voltage pulses. The input interface is configured to receive a control signal indicative of one or more time intervals. The input masking circuitry is configured to prevent the input current pulses from saturating the TIA during the one or more time intervals indicated by the control signal.

A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.

An amplifier transistor operates in two operation modes having different characteristics. A first bias circuit including a first bias supply transistor supplies an output current of the first bias supply transistor to the amplifier transistor as a bias current. A second bias circuit including a second bias supply transistor supplies a portion of an output current of the second bias supply transistor to the amplifier transistor as a bias current. At least one of the first bias circuit and the second bias circuit is selected and operates in accordance with an operation mode of the amplifier transistor by using a bias control signal input to a bias control terminal. The second bias circuit includes a current path along which a portion of the output current of the second bias supply transistor is returned to the second bias circuit.

A power amplifier and power amplification circuit are described herein. An illustrative power amplifier is disclosed to include an input terminal, a drive amplifier connected to the input terminal, and an impedance modulator having a capacitance that is adjusted inversely and proportionately relative to a signal output by the drive amplifier, wherein the impedance modulator provides a feedback loop between an output of the drive amplifier and the input terminal.

Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.

A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Memories for receiving or transmitting voltage signals might include an input or output buffer including a first stage having first and second inputs and configured to generate a current sink and source at its first and second outputs responsive to a voltage difference between its first and second inputs, and a second stage having a first input connected to the first output of the first stage, a second input connected to the second output of the first stage, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.

A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.

An amplifier circuit includes, a first transistor and a first resistor connected in series between a power supply voltage and an output terminal. A second transistor and a second resistor are connected in series between the output terminal and a ground reference voltage. There is a first operational amplifier and a second operational amplifier. A first detection current corresponding to a voltage drop across first resistor is generated. A second detection current corresponding to a voltage drop across the second resistor is generated. A first replication circuit subtracts the second detection current from the first detection current. A third resistor conducts the current obtained by subtracting the second detection current from the first detection current.