A new type of amplifier, herein designated a resource pooling amplifier, involves extended usage of one or more inductors that is implemented by sharing. The sharing is either by switching the inductor or inductors among more than one load terminal at the same time (e.g., a bridged configuration or two different loads terminals with different polarity requirements) or by using the inductor or inductors for more than one purpose at different times. The inductor or inductors may be time shared such as by allocating different phases of a clock. The inductor or inductors may also be shared by monitoring load requirements and using the inductor or inductors only when needed (leaving other inductor cycles for other loads). In addition, inductor sharing may be implemented during different application requirements such as if two or more loads are not needed at the same time in a system. These types of sharing may be combined.

A new type of amplifier, herein designated a resource pooling amplifier, involves extended usage of one or more inductors that is implemented by sharing. The sharing is either by switching the inductor or inductors among more than one load terminal at the same time (e.g., a bridged configuration or two different loads terminals with different polarity requirements) or by using the inductor or inductors for more than one purpose at different times. The inductor or inductors may be time shared such as by allocating different phases of a clock. The inductor or inductors may also be shared by monitoring load requirements and using the inductor or inductors only when needed (leaving other inductor cycles for other loads). In addition, inductor sharing may be implemented during different application requirements such as if two or more loads are not needed at the same time in a system. These types of sharing may be combined.

The present invention relates to a modulator for a digital amplifier and a device comprising such a modulator and a digital amplifier.

The modulator (100) comprises a pulse shaper (110) and a control unit (120) for controlling the pulse shaper (110) to convert an input signal into a bit stream (130) configured for a digital amplifier which encodes an amplitude value per clock of a carrier signal. The pulse shaper (110) can represent a respective amplitude value of the input signal with different bit patterns. The bit pattern respectively used by the pulse shaper is determined by the control unit (120) by means of a corresponding, associated control command. The modulator (100) is characterized in that in the control unit (120) an assignment (160) of the control commands to associated amplitude values resulting from amplification of the associated bit patterns with the digital amplifier (400) is stored or at least is provided in that the control unit (120) selects a control command per clock by means of the assignment (160) and the amplitude value of the input signal and drives the pulse shaper (110) accordingly.

A power conversion system comprising an amplifier input for receiving an analog input signal and an amplifier output for providing a switching output signal is disclosed. The system is applicable for use in high definition switching audio amplification. The power conversion system further comprises a clipper for clipping the analog input signal having a predefined range limited by a clipping level, a pulse modulator and a switching power stage. The system further has a feedback path to the clipper including a duty cycle measuring unit and a clip level filter which generates a clip level signal and where the clipping level of the clipper is controlled by the clip level signal. Hereby it is e.g. possible to clip an analog input signal with good precision and reliability in a switching power conversion system.

A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.

A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.

Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor.