An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.

The present invention discloses a class D amplifier chip with duty ratio limiting functions and the device thereof, a class D amplifier chip includes triangle wave modules, PWM modulation modules, duty ratio detection modules and logic control modules, the input differential audio signals and triangle wave signals generated by the triangle wave module are converted into low voltage pulsed PWM signals through the PWM modulation module, then gets driving processed and generates high voltage pulses; the duty ratio detection module real-time detects the duty ratio of PWM signals, when the logic control module decides the duty ratio of the PWM signals is larger than the preset maximum value, the PWM module is controlled to stop working, equals to close the audio output of the class D amplifier device; which limits the amplitude of the output audio signals, avoids burning the speaker due to an overlarge amplitude.

An apparatus for quantized linear amplification with nonlinear amplifiers that performs a linear amplification of variable-envelope single carrier (SC) or multi-carrier (MC) bandpass signals, based on sampled and quantized versions of its complex envelope, where the quantizer generates N.sub.b bits that are mapped into N.sub.mN.sub.b polar components, in which the quantized symbol can be decomposed, that are modulated as N.sub.m constant or quasi constant envelope signals and where each one is amplified by a nonlinear amplifier.

A Class D amplifier is described herein that includes an outer loop, an inner loop, and a notch filter. The notch filter can be located between an output of the outer loop and an input of the inner loop. Alternatively or in addition, the notch filter can be located within the outer loop of the Class D amplifier. Ripple content can initially be present at an input to the inner loop of the Class D amplifier, causing nonlinearity in the inner loop and distortion in the audio output signal. The notch filter can filter the ripple content at the input to the inner loop, thereby reducing the nonlinearity present in the inner loop and the distortion in the audio output signal.

An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Control circuitry may reduce audio artifacts associated with switching between modes.

An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.

A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.

A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.

The present disclosure relates to a class-D audio amplifier. When the class-D audio amplifier is powered on, an auxiliary power amplifier and an auxiliary feedback circuit constitute an auxiliary close loop so that a control loop is established in advance. The auxiliary close loop is disconnected after various circuit modules reach their steady operation points, and the class-D audio amplifier operates at a normal state. A soft start circuit is provided for suppressing noise which occurs when the class-D audio amplifier is powered on. Thus, the class-D audio amplifier suppresses POP noise at an output terminal when the class-D audio amplifier is powered on.

The present disclosure relates to a class-D audio amplifier. When the class-D audio amplifier is powered on, an auxiliary power amplifier and an auxiliary feedback circuit constitute an auxiliary close loop so that a control loop is established in advance. The auxiliary close loop is disconnected after various circuit modules reach their steady operation points, and the class-D audio amplifier operates at a normal state. A soft start circuit is provided for suppressing noise which occurs when the class-D audio amplifier is powered on. Thus, the class-D audio amplifier suppresses POP noise at an output terminal when the class-D audio amplifier is powered on.