A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.

A Class-D amplifier includes an analog-to-digital converter (ADC) having a first input node. The ADC receives a first analog input signal and a first feedback signal at the first input node and generates a first digital signal based on the first analog input signal and the first feedback signal. A digital filter generates a second digital signal based on the first digital signal. An output circuit includes a first output node, the output circuit being configured to generate a first output signal at the first output node based on the second digital signal. A first feedback unit generates the first feedback signal as the first output signal scaled by a gain factor having a constant value in the Z-domain.

Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, S.sub.IN, and a first clock signal f.sub.SW. The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability while reducing switching power losses.

A fully differential class-D amplifier having a controlled common-mode output voltage is disclosed. The differential class-D amplifier may include a correction circuit to determine the common-mode output voltage associated with differential pulse width modulated output signals and to generate differential correction signals to control the common-mode output voltage. In some exemplary embodiments, the differential class-D amplifier may include a plurality of gain stages to generate the differential PWM output signals. The differential correction signals may be provided to at least one stage of the differential class-D amplifier.

Systems and methods are provided for amplifying multiple input signals to generate multiple output signals. An example system includes a first channel, a second channel, and a third channel. The first channel is configured to receive one or more first input signals, process information associated with the one or more first input signals and a first ramp signal, and generate one or more first output signals. The second channel is configured to receive one or more second input signals, process information associated with the one or more second input signals and a second ramp signal, and generate one or more second output signals. The first ramp signal corresponds to a first phase. The second ramp signal corresponds to a second phase. The first phase and the second phase are different.

A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.

A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.

A variable ramp up/down gain in a pre-power stage block of an audio amplifier may be used to reduce audible pops and clicks output by the audio amplifier. A controller may adjust the variable ramp up/down gain during operation of the audio amplifier. The variable ramp up/down gain may be implemented as a pulse width modulation (PWM) modulator/generator with a ramp-up and ramp-down gain under control of the controller. The variable ramp up/down gain smooths transitions of the offset between a pre-power stage block and a feedback loop and thus can reduce audible pops and clicks by reducing the offset that is amplified in the power stage block of the audio amplifier.

Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.

Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.