A power amplifier includes an in-phase modulator configured to modulate an in-phase component of an input signal, a quadrature modulator configured to modulate a quadrature component of the input signal, and a processor configured to process the in-phase and quadrature components. The processor includes a clock configured to produce a clock signal, a pulse processor configured to remove non-essential information from the modulated in-phase and quadrature components, and a pulse converter configured to select an amplifier class and output a control signal based on the selected amplifier class. A switching network is also included and configured to actuate one or more switches based on the control signal to output an amplified signal.

An over charge protection method applied to a voltage converter which can operate in a quaternary modulation mode (Q mode) or a ternary modulation mode (T mode). The over charge protection method comprises: (a) determining whether the voltage converter operates in the Q mode or the T mode; and (b) setting a current threshold of the voltage converter to a first over current threshold if the voltage converter operates in the T mode; and (c) setting the current threshold to a second over current threshold if the voltage converter operates in the Q mode, wherein the first current threshold is smaller than the second over current threshold.

A system for processing a signal in a signal chain having decentralized embedded power management of components of the signal chain includes an input circuit to generate a measurement signal responsive to a stimulus, where the measurement signal is indicative of a characteristic of the stimulus. The system additionally includes a signal converter circuit coupled to the input circuit to convert the measurement signal to a digital signal according to a timing condition for capturing a sample of the measurement signal. The signal converter includes a control circuit to provide electrical power to the input circuit based on the timing condition and a sampling circuit to capture the sample of the measurement signal responsive to an indicator signal generated by the sensor circuit.

Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.

Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.

A capacitive-coupled chopper instrumentation amplifier includes a first chopper, a first gain stage, a capacitive isolation stage electrically coupled between inputs of the first gain stage and the first chopper, a second gain stage, a second chopper electrically coupled between outputs of the first gain stage and inputs of the second gain stage, clamping circuitry electrically coupled between the inputs of the first gain stage and a reference voltage rail, and a controller. The controller is configured to (a) detect a change in a first common-mode voltage exceeding a threshold value, the first common-mode voltage being a common-mode voltage at the inputs of the amplifier, and (b) in response to detecting the change in the first common-mode voltage exceeding the threshold value, cause the clamping circuitry to clamp the inputs of the first gain stage to the reference voltage rail.

A sensor arrangement for light sensing for light-to-frequency conversion. The sensor arrangement includes a photodiode, an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK1), and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing the digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of chopping switches coupled to a first amplifier, a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.