Embodiments of a power amplifier and method of operating a power amplifier are disclosed. In one embodiment, a power amplifier includes a pulse wave modulation (PWM) controller, a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller, a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller, and a mid-voltage control circuit configured to hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS and hold the voltage of the second output at the mid-voltage during an interval between when the first output is driven between VDD and VSS.

Systems and methods are provided for which a chopper modulator and a chopper demodulator of a chopped apparatus having a variable chopper frequency are described. A feedback path is used to reduce ripples and/or remaining offsets as a result of the variable chopper frequency.

Systems and methods are provided for which a chopper modulator and a chopper demodulator of a chopped apparatus having a variable chopper frequency are described. A feedback path is used to reduce ripples and/or remaining offsets as a result of the variable chopper frequency.

A circuit includes a comparator to compare an analog signal to a ramp signal to generate a pulse width modulated output signal and a driver to generate control signals for a plurality of power transistors. A pulse blanking circuit receives the pulse width modulated output signal. For each pulse of the pulse width modulated output signal, the pulse blanking circuit, responsive to a width of the pulse being greater than a threshold, passes the pulse to the driver. Responsive to the width of the pulse being less than the threshold, the pulse blanking circuit prevents the pulse from being passed to the driver.

A first module is configured to, based on an input sample, determine a first duty cycle. A second module is configured to, based on a battery voltage and the first duty cycle, determine a second duty cycle. A third module is configured to: set a scalar value based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage; and generate a start signal at a rate equal to a predetermined rate multiplied by the scalar value. A fourth module is configured to set a third duty cycle based on the second duty cycle and the scalar value. A fifth module is configured to generate a PWM output based on the start signal and the third duty cycle. A sixth module is configured to apply power to gates of FETs of a voltage converter based on the PWM output.

An amplifier circuit includes: a Schmidt trigger having an input electrically coupled to an input of the amplifier circuit, a switching network electrically coupled to an output of the Schmidt trigger, an inductor electrically coupled to the switching network, a first resistor electrically coupled to the inductor, a capacitor electrically coupled to the first resistor, a first feedback circuit that provides a first feedback signal to the input of the Schmidt trigger based on a voltage at a first node electrically coupled to the first resistor and to the capacitor, a second resistor electrically coupled to the output of the amplifier circuit, a third resistor electrically coupled to the second resistor, and a second feedback circuit that provides a second feedback signal to the input of the Schmidt trigger based on a voltage at a second node electrically coupled to the second resistor and to the third resistor.

A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

A chopper stabilized amplifier includes a first transconductance amplifier, first chopping circuitry coupled to an input of the first transconductance amplifier for chopping an input signal and applying the chopped input signal to the input of the first transconductance amplifier, and second chopping circuitry coupled to an output of the first transconductance amplifier for chopping an output signal produced by the first transconductance amplifier. A ping-pong notch filter is connected to an output of the second chopping circuitry and performs an integrate and transfer function on a chopped output signal produced by the second chopping circuitry to filter ripple voltages. The ping-pong notch filter includes parallel connected first and second notch filters, each of which has an input coupled to the output of the second chopping circuitry.

A chopper stabilized amplifier includes a first transconductance amplifier, first chopping circuitry coupled to an input of the first transconductance amplifier for chopping an input signal and applying the chopped input signal to the input of the first transconductance amplifier, and second chopping circuitry coupled to an output of the first transconductance amplifier for chopping an output signal produced by the first transconductance amplifier. A ping-pong notch filter is connected to an output of the second chopping circuitry and performs an integrate and transfer function on a chopped output signal produced by the second chopping circuitry to filter ripple voltages. The ping-pong notch filter includes parallel connected first and second notch filters, each of which has an input coupled to the output of the second chopping circuitry.

A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.