A power amplifier includes an input terminal configured to receive a low voltage input signal, an output terminal configured to output a high voltage output signal, and a plurality of amplifiers stacked in series between a first voltage terminal and a second voltage terminal. Each of the amplifiers includes an input capacitor, an output capacitor, an input coupled to the input terminal through the input capacitor, an output coupled to the output terminal through the output capacitor, and a feedback element coupled between the input and the output of the amplifier.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A radiofrequency (RF) amplifier includes an input terminal, an output terminal, and a power supply and biasing stage having an output coupled to the input terminal. An amplification stage of the RF amplifier includes a first transistor having a control terminal coupled to the input terminal and a first conduction terminal coupled to the output terminal. The power supply and biasing stage is configured to generate a bias voltage at the control terminal of the first transistor to simultaneously regulate a power supply voltage of the amplification stage to a first voltage and a bias current of the amplification stage to a first current.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

A capacitive gain amplifier circuit amplifies an input signal by a pair of differential amplifier circuits couples in series. The first differential amplifier circuit is reset during an autozero phase while disconnected from the second differential amplifier circuit, and the first and second differential amplifier circuits are connected together in series during a chop phase. A set of feedback capacitors is selectively switched in between respective outputs of the second differential amplifier circuit and respective inputs of the first differential amplifier circuit during the chop phase.

An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.