A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.

The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

An electronic circuit is provided. The electronic circuit includes a first current generating circuit configured to output a first operating current based on a first operating voltage; and an input circuit configured to: receive a first current corresponding to a first input voltage and a second current corresponding to a second input voltage, wherein the first current and the second current are based on the first operating current; receive a third current and a fourth current that are generated based on the first operating voltage; and generate a fifth current corresponding to the second input voltage based on a second operating current. The electronic circuit is configured to generate an output voltage that is associated with a difference between the first input voltage and the second input voltage based on the second current, the fourth current and the fifth current, and the fourth current corresponds to the third current.

A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.

A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.

Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.

An envelope tracking method and device are provided. The envelope tracking method includes: acquiring, by a boost circuit, a target envelope tracking input current signal, and transmitting, by the boost circuit, the target envelope tracking input current signal to an amplifier circuit, where the amplifier circuit includes an operational amplifier and a feedback network, and the operational amplifier operates in a mode of floating ground; and performing, by the amplifier circuit, closed-loop conversion and amplification on the target envelope tracking input current signal and outputting, by the amplifier circuit, an envelope tracking output voltage.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

Automated power noise susceptibility test systems are provided for one or more storage devices. A system includes a host; storage devices; and multiple noise injection modules. Each noise injection module includes: a first relay to a third relay, which are coupled to a first path or a second path. The first path includes: an operational amplifier for generating a high noise function; a first variable regulator for generating a first or second regulated power supply voltage; and a capacitor injection circuit for generating low noise function and a first power noise. The second path includes: a second variable regulator for generating a third or fourth regulated power supply voltage and a power amplifier injection circuit for generating a second power noise. The third relay selectively provides the storage device the first power noise or the second power noise.