A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.

A radio-frequency (RF) push-pull amplifier circuit that includes: a first transistor; a transformer; and a first matching circuit comprising at least one capacitor and at least one inductor, in which an input of the first matching circuit is coupled to an output of the first transistor, an output of the first matching circuit is coupled to an input of the transformer, and the first matching circuit is configured to transform an impedance at the input of the transformer into a first predefined impedance at the output of the first transistor.

In accordance with an embodiment, a circuit includes an amplifier and a programmable capacitor coupled between an output of the first non-inverting and the input of the first amplifier.

Voltage regulators and related methods are described. The voltage regulators described in the application may include an operational amplifier, an output transistor, and a signal buffer connected between the operational amplifier and the output transistor. In some embodiments, these voltage regulators are used in connection with memory units. A voltage regulator may be arranged such that the signal amplifier clamps the voltage at the gate of the output transistor to the output voltage when the memory unit is in an idle mode. In this way, when the memory is accessed, the amplitude and duration of output voltage overshoots can be limited, relative to some voltage regulators.

A display driver includes a digital-to-analog (D/A) converting circuit, an inverting amplifier circuit, and current compensating circuits. The D/A converting circuit converts display data into a gradation voltage. The inverting amplifier circuit includes an operational amplifier, a resistor provided between an input node to which the gradation voltage is input and an inverting input terminal of the operational amplifier, and a resistor provided between an output terminal of the operational amplifier and the inverting input terminal. The current compensating circuit causes a compensation current to flow from a first node of a first supply voltage to an input node. The current compensating circuit causes a compensation current to flow from the input node to a second node of a second supply voltage.

A current Iin is separated into currents I1 and I2. When I1 flows in a light emitting diode D1, the diode D1 emits light and the current path of a phototransistor Q1 becomes conductive. At that time, current Iout flows in a light emitting diode D2. When the diode D2 emits light, the current path of a phototransistor Q2 becomes conductive, and I2 flows. If the value of the current Iout is large, the light emitting strength of the diode D2 is large. A large current I2 flows in the phototransistor Q2, which decreases the value of the current I1 flowing in the diode D1. As a result, the light emitting strength of the diode D1 becomes small, and the value of the current Iout decreases. In this manner, since a photocoupler P2 functions as a negative feedback circuit, linearity of the current Iin and the current Iout improves.

An amplifier circuit has a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer and a signal node for receiving the input signal. An amplifier arrangement comprising a feedback resistor network provides an amplified output signal. A voltage buffer provides a buffered bias voltage at a buffer node which is connected to a terminal of the feedback resistor network, to at least partly define the quiescent level of the output signal. The buffer node is electrically coupled to the transducer biasing node via a capacitance which may form part of a bias filter.

The electronic circuit having an input stage for pre-amplifying an electrical input signal of the electronic circuit provided by a transducer. The electronic circuit has an output stage for providing a microphone output signal by processing an output signal of the input stage. The electronic circuit has an adjustable output load arranged and configured for setting a current draw of the output stage. Additionally, the electronic circuit has a measurement circuit configured to capture the output signal of the input stage and an automatic control circuit configured to adjust the adjustable output load dependent on the captured output signal of the input stage.