A semiconductor integrated circuit includes a first pad provided on one end side of a first resistive element and one end side of a second resistive element externally provided, a second pad provided on a different end side of the first resistive element, a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided, an operation amplifier, a first signal line, wired between an output terminal of the operation amplifier and the first pad, a second signal line wired between an inverting input terminal of the operation amplifier and the second pad, a third signal line wired between the inverting input terminal of the operational amplifier and the third pad, a first ESD protection element, provided to the first signal line, a fourth signal line, through which a voltage signal of the first pad.

A semiconductor integrated circuit includes a first pad provided on one end side of a first resistive element and one end side of a second resistive element externally provided, a second pad provided on a different end side of the first resistive element, a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided, an operation amplifier, a first signal line, wired between an output terminal of the operation amplifier and the first pad, a second signal line wired between an inverting input terminal of the operation amplifier and the second pad, a third signal line wired between the inverting input terminal of the operational amplifier and the third pad, a first ESD protection element, provided to the first signal line, a fourth signal line, through which a voltage signal of the first pad.

An amplifier circuit includes a first transistor; a first resistor to which a first potential is applied, the first resistor being connected to an emitter of the first transistor; a second resistor to which a second potential is applied, the second resistor being connected to a collector of the first transistor; and a signal control circuit configured to apply, to a base of the first transistor, a voltage that has been level-shifted based on an average value of a voltage at the collector of the first transistor, the signal control circuit being provided between the collector and the base of the first transistor.

A first circuit unit of an audio amplifier includes a first emitter follower connected to an pre stage input terminal, a second emitter follower connected to an pre stage input terminal, a main transistor connected to an output path of the first emitter follower and an output path of the second emitter follower, a first resistor and a second resistor, which are series-connected between the output path of the first emitter follower and a DC voltage source, and a zener diode connected to a series-connection point between the first resistor and the second resistor. A second circuit unit has a circuit configuration that is complementary to the first circuit unit. A path leading to a collector of each transistor configuring the first and second emitter followers in one of the circuit units is connected to the series-connection point in the other circuit unit.

An input stage of a chip includes a source driver and a sensing and clamping circuit. The source follower is arranged for receiving an AC-coupled signal to generate an output signal at an output terminal. The sensing and clamping circuit is coupled to the source follower, and is arranged for clamping the output terminal of the source follower at a fixed DC voltage.

A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2 Vbe) of the amplifying transistor.

A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2 Vbe) of the amplifying transistor.

A transconductance circuit has an input terminal (V.sub.IN) and an output terminal (Out), a first current source (4) having a gate connected to said input terminal (V.sub.IN); and a second current source (5), in parallel with said first current source, and having a higher transconductance and a wider dynamic range than the first current source. The current sources are configured so that at a low input voltage only the first current source (4) is on. A voltage drop circuit provides a lower bias voltage for the second current source than for the first current source.

In an example apparatus, a first transistor has a base terminal, a first current terminal and a second current terminal. The base terminal is coupled to an input voltage node. A second transistor has a control terminal, a third current terminal and a fourth current terminal. The third current terminal is coupled to the second current terminal. The fourth current terminal is coupled to a first resistor. A second resistor is coupled to the control terminal. An inductor is coupled between the first resistor and a ground terminal.

A method and an apparatus for generating a particle wave carrying an electric charge is provided. The method comprises: on the basis of waveform information pre-stored in a waveform storage module, generating a corresponding digital waveform signal; the waveform information comprising amplitude and phase; on the basis of a digital-to-analog conversion module connected to the waveform storage module, converting the digital waveform signal having a pre-set phase into an analog waveform signal; on the basis of a power amplification module connected to the digital-to-analog conversion module, performing power amplification on the analog waveform signal; on the basis of a high-voltage generator connected to the power amplification module, performing high-voltage amplification on the power signal of the analog waveform signal; and by means of a quasi-continuous emission electrode connected to the high-voltage generator, emitting a charged particle wave on the basis of the analog waveform voltage signal.