A system for optical data interconnect of a source and a sink includes a first HDMI compatible electrical connector able to receive electrical signals from the source. A first signal converter is connected to the first HDMI compatible electrical connector and includes electronics for conversion of TMDS or FRL electrical signals to optical signals, with the electronics including an optical conversion device. At least one optical fiber is connected to the first signal converter. A second signal converter is connected to the at least one optical fiber and includes electronics for conversion of optical signals to differential electrical signals. A power module for the second signal converter includes a power tap connected to TMDS or FRL circuitry and a first voltage regulator connected to the power tap to provide power to an electrical signal amplifier. A rechargeable battery module is used to trigger power activation of connected ports, with the battery module being connected to the power tap. A second HDMI compatible electrical connector is connected to the second signal converter and able to send signals to the sink.

A system for optical data interconnect of a source and a sink includes a first HDMI compatible electrical connector able to receive electrical signals from the source. A first signal converter is connected to the first HDMI compatible electrical connector and includes electronics for conversion of TMDS or FRL electrical signals to optical signals, with the electronics including an optical conversion device. At least one optical fiber is connected to the first signal converter. A second signal converter is connected to the at least one optical fiber and includes electronics for conversion of optical signals to differential electrical signals. A power module for the second signal converter includes a power tap connected to TMDS or FRL circuitry and a first voltage regulator connected to the power tap to provide power to an electrical signal amplifier. A rechargeable battery module is used to trigger power activation of connected ports, with the battery module being connected to the power tap. A second HDMI compatible electrical connector is connected to the second signal converter and able to send signals to the sink.

A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.

An amplifier includes a first stage and a second stage. The first stage is configured to amplify a received signal. The second stage is coupled to the first stage. The second stage includes a source follower and a compensation network. The source follower includes an input and an output. The compensation network is coupled to the input of the source follower and the output of the source follower. The compensation network is configured to modify a magnitude and phase response of the first stage based on a load capacitance coupled to the output of the source follower.

A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.

A reset signal is generated by a TIA circuit alone. In an embodiment, a transimpedance amplifier configured to convert a current signal into a voltage signal includes a transimpedance stage including an amplification stage constituted of a transistor with a grounded emitter, and a comparator configured to compare a collector voltage of the transistor with a reference voltage and output a reset signal.

Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (M.sub.p) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (M.sub.c) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−g.sub.mf) comprising an input terminal and an output terminal. The first terminal of the first transistor (M.sub.p) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (M.sub.p) is coupled with the first terminal of the second transistor (M.sub.c) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−g.sub.mf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−g.sub.mf).

A power amplifier and power amplification circuit are described herein. An illustrative power amplifier is disclosed to include an input terminal, a drive amplifier connected to the input terminal, and an impedance modulator having a capacitance that is adjusted inversely and proportionately relative to a signal output by the drive amplifier, wherein the impedance modulator provides a feedback loop between an output of the drive amplifier and the input terminal.

A power amplifier and power amplification circuit are described herein. An illustrative power amplifier is disclosed to include an input terminal, a drive amplifier connected to the input terminal, and an impedance modulator having a capacitance that is adjusted inversely and proportionately relative to a signal output by the drive amplifier, wherein the impedance modulator provides a feedback loop between an output of the drive amplifier and the input terminal.