Described herein are load-modulated balanced amplifiers. An example load-modulated balanced amplifier can include a radio frequency (RF) input port, a RF output port, a peaking amplifier circuit operably coupled between the RF input and RF output ports, where the peaking amplifier circuit is a balanced amplifier that includes a pair of power amplifiers, and a carrier amplifier circuit operably coupled to the RF input port.

There is presented a wireless device for dual-polarization beamforming. The wireless device comprises an antenna array. The antenna array comprises antenna elements of mutually orthogonal polarizations and a baseband chain. The antenna elements of both polarizations are operatively connected to the baseband chain. There is also presented a method for dual-polarization beamforming as performed by such a wireless device.

In accordance with the embodiments of the present disclosure, a rack comprising a frame having first vertical posts on a first side and second vertical posts on a second side, between which a plurality of RF amplifier modules are mounted, is provided. The RF power outputs of the RF amplifier modules are connected to inputs of an RF power combiner to deliver a combined RF power output. The RF power combiner is arranged at least partially in at least one of a first volume between the first vertical posts of the frame or a second volume between the second vertical posts of the frame, thereby reducing a footprint of the rack.

The present disclosure relates to the field of amplifier circuits (driver amplifiers) for electro-optical modulators, in particular for amplifying an electrical signal for driving electro-optical modulators, an amplifier circuit is proposed for amplifying a signal comprising a gain amplifier, a distributed amplifier, a resistor, and a current source, wherein the input of the distributed amplifier is electrically connected to the output of the gain amplifier; the resistor terminates the input of the distributed amplifier; and the current source is electrically connected in parallel to the resistor. A method of setting a bias voltage of such an amplifier circuit is also proposed. Furthermore, a transmitter, in particular an optical transmitter, comprising such an amplifier circuit and a system comprising such a transmitter and a signal source are also proposed.

A consecutive Doherty amplifier is disclosed. The Doherty amplifier includes a carrier amplifier, a power splitter, a peak amplifier, and a phase compensator. The carrier amplifier receives a radio frequency signal with interposing any signal splitters. The power splitter splits an output of the carrier amplifier into first and second split signals. The phase compensator transfers the second split signal to the peak amplifier. The first split signal is combined with the output of the peak amplifier.

Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.

In certain aspects, a receiver includes first amplifiers, wherein each one of the first amplifiers comprises an input and an output. The receiver also includes second amplifiers, wherein each one of the second amplifiers comprises an input and an output, and the outputs of the second amplifiers are coupled to a combining node. The receiver also includes transmission lines, wherein each one of the transmission lines is coupled between the output of a respective one of the first amplifiers and the input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and receiver elements, wherein each one of the receiver elements comprises an input and an output, and the output of each one of the receiver elements is coupled to the input of a respective one of the first amplifiers.

A radio frequency circuit has an amplifier that amplifies an input radio frequency signal, a power supply path that is disposed between an output node of the amplifier and a power supply node to which a DC bias voltage is supplied, and includes a first inductor and a second inductor connected in series, a first resonator that comprises a third inductor and a first capacitor connected in series to the third inductor, and resonates at a series resonance frequency, a second resonator that resonates at a series resonance frequency corresponding to an inductance of the first inductor, a capacitance of the second capacitor, and a resistance value of the first resistor, and a third resonator that comprises a third capacitor connected in parallel with the second inductor, and resonates at a parallel resonance frequency corresponding to a capacitance of the third capacitor and an inductance of the second inductor.

A harmonic trap filter suppresses at least one harmonic signal produced by an amplifier and includes an input terminal and a ground terminal. The harmonic trap filter further includes a plurality of resonators electrically coupled one to another between the input terminal and the ground terminal in a spatial order defined by relative phase shift of alternating voltage bias signals respectively applied thereto. The resonators are tuned to resonate at a frequency at which a phase delay is imparted to the at least one harmonic signal by the resonators to effect cancelation of the at least one harmonic signal at the input terminal.

A harmonic trap filter suppresses at least one harmonic signal produced by an amplifier and includes an input terminal and a ground terminal. The harmonic trap filter further includes a plurality of resonators electrically coupled one to another between the input terminal and the ground terminal in a spatial order defined by relative phase shift of alternating voltage bias signals respectively applied thereto. The resonators are tuned to resonate at a frequency at which a phase delay is imparted to the at least one harmonic signal by the resonators to effect cancelation of the at least one harmonic signal at the input terminal.