A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

According to various embodiments, an electronic device may include: a communication processor, a radio frequency (RF) integrated circuit (RFIC) configured to receive a signal output from the communication processor and to modulate the signal into an RF signal, a power management circuit, a first power amplifier configured to amplify an RF signal output from the RFIC based on power supplied from the power management circuit, a second power amplifier configured to amplify the RF signal output from the RFIC based on the power supplied from the power management circuit, at least one capacitor connected in parallel to a power supply terminal of the first power amplifier, and at least one switch connected between the power supply terminal and the at least one capacitor, wherein the communication processor is configured to: identify a power amplification mode based a frequency band of the RF signal, and control the at least one switch by outputting a control signal corresponding to the identified power amplification mode.

A radio frequency front-end is disclosed having a first power amplifier (PA) having a first PA input and a first PA output, a second PA having a second PA input and a second PA output, and a low-noise amplifier (LNA) having an LNA output connected to a receive output terminal and an LNA input. An input 90° hybrid coupler has a first port input connected to a transmit terminal, a second port input connected to a fixed voltage node through an isolation impedance, a third port output connected to the first amplifier input and a fourth port output connected to the second amplifier input. An output 90° hybrid coupler has a first port output connected to a common terminal, a second port output connected to the LNA input, a third port input connected to the second PA output, and a fourth port input connected to the first PA output.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a “common source” configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.

Devices and systems useful in concurrently receiving and transmitting Wi-Fi signals and Bluetooth signals in the same frequency band are provided. By way of example, an electronic device includes a transceiver configured to transmit data and to receive data over channels of a first wireless network and a second wireless network concurrently. The transceiver includes a plurality of filters configured to allow the transceiver to transmit the data and to receive the data in the same frequency band by reducing interference between signals of the first wireless network and the second wireless network.

Devices and systems useful in concurrently receiving and transmitting Wi-Fi signals and Bluetooth signals in the same frequency band are provided. By way of example, an electronic device includes a transceiver configured to transmit data and to receive data over channels of a first wireless network and a second wireless network concurrently. The transceiver includes a plurality of filters configured to allow the transceiver to transmit the data and to receive the data in the same frequency band by reducing interference between signals of the first wireless network and the second wireless network.

A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.