A power amplifier module includes an output-stage amplifier, a driver-stage amplifier, an input switch, an output switch, an input matching circuit, an inter-stage matching circuit, an output matching circuit, and a control circuit. The input switch selectively connects one of a plurality of input signal paths to an input terminal of the driver-stage amplifier. The output switch selectively connects one of a plurality of output signal paths to an output terminal of the output-stage amplifier. The control circuit controls operations of the driver-stage amplifier and the output-stage amplifier. The input switch, the output switch, and the control circuit are integrated into an IC chip. The control circuit is disposed between the input switch and the output switch.

In some embodiments, radio-frequency amplifiers can include a plurality of narrow band power amplifiers implemented. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.

In some embodiments, radio-frequency amplifiers can include a plurality of narrow band power amplifiers implemented. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.

A transceiver includes a first common T-coil circuit coupled to a first input-output pin of the transceiver, a termination impedance coupled to the first common T-coil circuit and configured to match an impedance of a transmission line coupled to the first common T-coil circuit, an amplifier configured to receive an input signal from the first input-output pin through the first common T-coil circuit based on a receive enable signal, and a first transmission buffer configured to transmit an output signal to the first input-output pin through the first common T-coil circuit based on a transmit enable signal.

An amplifier may include multiple stages, with the multiple stages arranged in a fan-out configuration. The fan-out configuration provides multiple amplified signals at multiple amplifier output nodes, which may be coupled to a shared set of downconverters. The shared downconverters may support processing of only a smaller bandwidth than the largest possible bandwidth of an input RF signal input to the amplifier. For example, the downconverters may support a bandwidth matching a smallest bandwidth of a supported RF signal. For example, when the amplifier is intended to support 5G mmWave RF signals and 5G sub-6 GHz RF signals, the downconverters may each individually support a bandwidth of carriers in the 5G sub-6 GHz RF signals but not individually support the entire bandwidth of a possible 5G mmWave RF signal.

Low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes an input balun configured to convert a single-ended radio frequency (RF) receive signal to a differential RF receive signal, an amplifier chain configured to amplify the differential RF receive signal to generate a differential amplified RF receive signal, and an output balun configured to convert the differential amplified RF receive signal into a single-ended amplified RF receive signal. The LNA's amplifier chain is operable in multiple gain modes, and includes a first differential amplification stage, a second differential amplification stage, and a third differential amplification stage.

An auxiliary control circuit (100) for a power amplification module, a power amplification module, and a communication device. The auxiliary control circuit (100) for the power amplification module comprises a main control chip (201), a current detection chip (12), and a precision adjustment unit (14). The precision adjustment unit (14) is connected in parallel to a precision control resistor of the current detection chip (12), and a switch control terminal of the precision adjustment unit (14) is electrically connected to the main control chip (201) and is used for adjusting an output voltage amplification factor of the current detection chip (12) when a switch signal outputted by the main control chip (201) is received. A detection input terminal of the current detection chip (12) is used for accessing a voltage to be measured of a power amplifier transistor power supply circuit (102) of the power amplification module. A detection output terminal of the current detection chip (12) is electrically connected to the main control chip (201). The main control chip (201) is used, upon receipt of a voltage signal outputted by the current detection chip (12), to measure and calculate so as to obtain a power amplification current corresponding to the voltage to be measured. By providing the precision adjustment unit (14) on the power amplification module for cooperation with the main control chip (201) and the current detection chip (12), the effect of greatly improving the detection precision of a power amplification current is achieved.

An auxiliary control circuit (100) for a power amplification module, a power amplification module, and a communication device. The auxiliary control circuit (100) for the power amplification module comprises a main control chip (201), a current detection chip (12), and a precision adjustment unit (14). The precision adjustment unit (14) is connected in parallel to a precision control resistor of the current detection chip (12), and a switch control terminal of the precision adjustment unit (14) is electrically connected to the main control chip (201) and is used for adjusting an output voltage amplification factor of the current detection chip (12) when a switch signal outputted by the main control chip (201) is received. A detection input terminal of the current detection chip (12) is used for accessing a voltage to be measured of a power amplifier transistor power supply circuit (102) of the power amplification module. A detection output terminal of the current detection chip (12) is electrically connected to the main control chip (201). The main control chip (201) is used, upon receipt of a voltage signal outputted by the current detection chip (12), to measure and calculate so as to obtain a power amplification current corresponding to the voltage to be measured. By providing the precision adjustment unit (14) on the power amplification module for cooperation with the main control chip (201) and the current detection chip (12), the effect of greatly improving the detection precision of a power amplification current is achieved.

Apparatuses, systems, and methods for implementing a multi-driver architecture are described. The multi-driver architecture may include a first driver and a second driver configured to receive an input voltage. A predriver logic circuit may select one of the first driver and the second driver to convert the input voltage into an output voltage. A controller may be connected to the first driver and the second driver, and a switch may be connected between an output terminal of the first driver and the controller. The controller may be configured to control an internal resistance of the switch. In response to the first driver being selected by the predriver logic circuit, the first driver may output the output voltage at a constant impedance level.

A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.