H03F2200/09

WIDEBAND LOW NOISE AMPLIFIER (LNA) WITH A RECONFIGURABLE BANDWIDTH FOR MILLIMETER-WAVE 5G COMMUNICATION
20190372533 · 2019-12-05 ·

According to one embodiment, a low noise amplifier (LNA) circuit includes a first stage which includes: a first transistor; a second transistor coupled to the first transistor; a first inductor coupled in between an input port and a gate of the first transistor; and a second inductor coupled to a source of the first transistor, where the first inductor and the second inductor resonates with a gate capacitance of the first transistor for a dual-resonance. The LNA circuit includes a second stage including a third transistor; a fourth transistor coupled between the third transistor and an output port; and a passive network coupled to a gate of the third transistor. The LNA circuit includes a capacitor coupled in between the first and the second stages, where the capacitor transforms an impedance of the passive network to an optimal load for the first amplifier stage.

AMPLIFIER MODULE
20240113666 · 2024-04-04 ·

An amplifier module includes an input terminal; a first preamplifier formed in or on a first substrate and configured to amplify a signal that is input to the input terminal; a first postamplifier and a second postamplifier that are formed in or on a second substrate and that are configured to receive an output of the first preamplifier and output a differential signal; an output balun configured to receive the differential signal that is output from the first postamplifier and the second postamplifier; and a variable capacitance element. The output balun includes a primary winding subjected to the differential signal and a secondary winding, and the variable capacitance element is connected in parallel with the primary winding of the output balun.

SYSTEM AND METHOD FOR BI-DIRECTIONAL RADIO COMMUNICATION

Apparatus and methods for performing wireless communications are provided. In some embodiments, an apparatus includes a transformer including a first winding, a second winding, and a third winding. The apparatus also includes a first transmitter circuit coupled with the first winding, and a second circuit coupled with the second winding. The third winding is coupled with an antenna. The first transmitter circuit is configured to transmit a first signal to the antenna via magnetic coupling between the first winding and the third winding. The second circuit is configured to tolerate without damage a second signal from the first transmitter circuit, wherein the second signal is generated from the first signal via magnetic coupling between the first winding and the second winding. A turn ratio between the first winding and the second winding can be configured to limit a voltage of the second signal to be within a pre-determined threshold.

Ultra wideband transmitter

Aspects described herein include devices and methods for smart ultra wideband transmissions. In one aspect, an apparatus includes pulse generation circuitry configured to output a plurality of transmission (TX) pulse samples at a selected signal sample rate, where each pulse sample of the plurality of TX pulse samples comprises a value associated with a pulse amplitude at a corresponding sample time The apparatus includes a plurality of power amplifier (PA) cells, with each PA cell of the plurality of PA cells comprising a corresponding current source and associated gates, and where the associated gates of a PA cell are selectable to configure an on state and an off state. Logic circuitry of the apparatus is configured to set the on state or the off state for each PA cell.

Balun and amplifier including balun

A balun configured for a power range between 500 W and 5 kW output includes a balanced signal port comprising a first connection and a second connection and further includes a single-ended signal port comprising a third connection and a fourth connection, the fourth connection being connected to ground. In addition, the balun includes a first capacitor disposed between the first connection and a first end of a first resistor and a second capacitor disposed between the second connection and the first end of the first resistor. A second end of the first resistor is connected to ground.

WIDE DYNAMIC RANGE AMPLIFIER SYSTEM

Amplifier systems and methods are provided that include a fixed gain amplification stage coupled to an adjustable attenuation stage further coupled to a variable gain amplification stage. A controller controls an amount of attenuation provided by the adjustable attenuation stage and an amount of gain provided by the variable gain amplification stage to maintain any of various noise, efficiency, and/or linearity requirements of the amplifier system.

Temperature Dependency Compensation
20190326859 · 2019-10-24 ·

An apparatus is disclosed that implements temperature dependency compensation. In an example aspect, the apparatus includes an amplifier, a transformer, a compensation component, and a bias circuit. The amplifier is configured to amplify a wireless signal to produce an amplified wireless signal. The transformer, which includes an inductor, is coupled to the amplifier and is configured to condition the amplified wireless signal. The compensation component is coupled in series with the inductor. The compensation component includes a compensation transistor that is configured to operate in at least one of a positive temperature-dependence range or a negative temperature-dependence range. The bias circuit includes a bias node that is coupled to the compensation transistor. The bias circuit is configured to cause the compensation transistor to operate in the positive temperature-dependence range or the negative temperature-dependence range.

Apparatus and method for improving efficiency of power amplifier

Embodiments of the disclosure generally relate to a method and device for improving the efficiency of a power amplifier. The apparatus comprising: a harmonic generator, configured to generate one or more harmonic according to an output signal of a power amplifier; a harmonic feedback device, configured to inject the harmonic generated by the harmonic generator to an input terminal of the power amplifier; and a harmonic eliminator, configured to eliminate the harmonic in the output signal of the power amplifier. According to embodiments of the disclosure, the efficiency of power amplifier can be improved without degrading the linearity.

METHOD TO IMPROVE POWER AMPLIFIER OUTPUT RETURN LOSS AND BACK-OFF PERFORMANCE WITH RC FEEDBACK NETWORK
20190312360 · 2019-10-10 ·

An apparatus includes a plurality of transceiver circuits and a plurality of feedback networks. Each of the plurality of transceiver circuits may be coupled to a respective antenna element in a respective group of antenna elements of a phased array antenna. Each of the transceiver circuits generally comprises a power amplifier circuit configured, when operating in a transmit mode, to drive the respective antenna element in the respective group of antenna elements. Each of the plurality of feedback networks may be coupled between an output and an input of a respective power amplifier circuit of a respective transceiver circuit. Each of the feedback networks generally comprises a resistor and a capacitor connected in series. The respective power amplifier circuit with the feedback network generally maintains a power matching condition with load variation associated with the antenna elements of the phased array antenna.

DIFFERENTIAL DOHERTY AMPLIFIER CIRCUIT
20240146251 · 2024-05-02 ·

A differential Doherty amplifier circuit includes a first differential amplifier including a first carrier amplifier and a second carrier amplifier, a second differential amplifier including a first peak amplifier and a second peak amplifier, a first line connected to the first carrier amplifier and the first peak amplifier, and a second line connected to the second carrier amplifier and the second peak amplifier. The first differential amplifier and the second differential amplifier are formed on a die of a chip device parallel to an XY plane. The first line and the second line are each formed of a wiring line disposed in a substrate parallel to the XY plane. The chip device is flip-chip mounted on the substrate in a Z direction orthogonal to the XY plane.