A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

Systems, methods, and devices relate to tunable baluns for multimode power amplification. For example, a variable-gain amplification system can include a power amplifier configured to provide an amplified signal and to selectively operate in at least a first gain mode and a second gain mode. The variable-gain amplification system can also include a tunable balun circuit configured to receive the amplified signal from the power amplifier and to provide an output signal. The tunable balun circuit can be configured to implement a first turn ratio for the first gain mode and a second turn ratio for the second gain mode.

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

A transformer is provided. The transformer includes at least one first primary turn; at least one second primary turn; and a first secondary turn and a second secondary turn. The first secondary turn and the second secondary turn are arranged laterally between the at least one first primary turn and the at least one second primary turn. The first secondary turn and the second secondary turn are arranged one above the other.

According to one embodiment, a transformer-based in-phase and quadrature (IQ) includes a differential balun having a first inductor and a second inductor. The first inductor has a first input terminal and a first output terminal. The second inductor has a second input terminal and a second output terminal. Additionally, the IQ generator circuit includes a third inductor magnetically coupled with the first inductor. The third inductor has a first isolation terminal and a third output terminal. The IQ generator circuit also includes a fourth inductor magnetically coupled with the second inductor. The fourth inductor has a second isolation terminal and a fourth output terminal. The IQ generator circuit additionally includes a first transistor coupled to the first input terminal of the first inductor. Further, the generator circuit includes a second transistor coupled to the second input terminal of the second inductor. The first transistor, the second transistor, the first inductor, and the second inductor form a part of a differential amplifier.

A higher-speed operation of a power amplifier circuit is achieved. A power amplifier circuit includes multi-stage amplifier units, an ET terminal, and an APT terminal. The multi-stage amplifier units include a final-stage amplifier unit. The final-stage amplifier unit includes a first amplifier element and a second amplifier element that are connected in parallel with each other. The first amplifier element is connected to the ET terminal. The second amplifier element is connected to the APT terminal.

An input driver includes a power converting unit and a level adjusting unit. The power converting unit is configured to generate a first power and a second power having an anti-phase relationship based on input power, and process the first power and the second power as differential inputs to output a third power. The level adjusting unit is configured to adjust a voltage level of the third power and output the adjusted power as an input to a power amplifier.

An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

A transformer includes: a primary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances; and a secondary winding electromagnetically coupled with the primary winding, the secondary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.