Embodiments disclosed herein generally relate to power amplifier matching circuits used for matching impedance and harmonic control in a device, such as a cellular phone. In one example, a power amplifier matching circuit includes two DVCs, four inductors, a transistor, and a capacitor. Utilizing the two DVCs, the impedance matching ratio and the center frequency of the circuit are capable of adjustment as needed. Moreover, the inclusion of the two DVCs may also prevent harmonic frequencies from undesirably passing through the power amplifier matching circuit to the antenna of a cellular device. The power amplifier matching circuit may be used in conjunction with an amplifier, where the output of the amplifier is proportional to the current in the circuit.

A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.

A power amplifier circuit for broadband data communication over a path in a communication network can reduce or avoid gain compression, provide low distortion amplification performance, and can accommodate a wider input signal amplitude range. A dynamic variable bias current circuit can be coupled to a common emitter bias node of a differential pair of transistors to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal. Bias current is increased when input signal amplitude exceeds a threshold voltage established by an offset or level-shifting circuit. The frequency response of the bias current circuit can track the frequency content of the input signal. A delay in the signal path to the differential pair can phase-align the bias current to the amplification by the differential pair. A dynamic variable supply voltage can be based on an envelope of the input signal.

The disclosed system and method provide for a CATV power amplifier in which power dissipation may be reduced by dynamically adjusting the amplifier bias such that the bias is high only when high peak output signals need to be produced. By combining a bias control signal and an RF data signal into a single signal produced by a single DA converter, the disclosed examples require fewer DA converters and a need to synchronize DA converters to produce each of the signals individually is eliminated. A low frequency signal may be added to the RF band to find an optimum compromise between positive and negative peak excursions produced by the amplifier such that an overall reduction in bias may be achieved.

An envelope signal time delay adjustment apparatus includes a negative group delay unit for converting an envelope signal input from a signal generator into an envelope signal having a group delay of a negative value whose frequency increases from a predetermined frequency band; an envelope-tracking modulator for power-amplifying and outputting the envelope signal output from the negative group delay unit; and a frequency limiting unit for limiting a bandwidth of the envelope-tracking modulator to be lower than an original bandwidth of the envelope-tracking modulator.

A transmitter comprising a power amplifier, a phase modulator, a switched DC-DC converter, all operating in dual mode, and a controller is disclosed. The power amplifier is arranged to selectively operate either in a first mode or in a second mode, wherein the first mode is a linear mode and the second mode is a non-linear mode in order to save power with least increasing cost in hardware. The transmitter is adapted to operate at different allocated bandwidths, for different radio standards while keeping minimum power consumption governed by the controller. A transceiver, a communication device, a method and a computer program are also disclosed.

Power amplification system with adaptive bias control. In some embodiments a power amplification system includes a power amplifier including a radio-frequency (RF) input terminal for receiving an RF signal, an RF output terminal for providing an amplified RF signal, a supply voltage terminal for receiving a power amplifier supply voltage to power the power amplifier, and one or more bias terminals for receiving one or more bias signals. The power amplification system also includes a bias controller configured to provide the one or more bias signals to the one or more bias terminals, at least one of the one or more bias signals being based on the power amplifier supply voltage.

Power amplifier modules with controllable envelope tracking noise filters are provided herein. In certain embodiments, an envelope tracking system includes a power amplifier module and an envelope tracker that provides the power amplifier module with a power amplifier supply voltage that changes based on an envelope of a radio frequency (RF) signal amplified by the power amplifier module. The power amplifier module includes a controllable filter that filters the power amplifier supply voltage to provide flexibility in filtering envelope tracking noise.

Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.