Dual-output power converter circuitry includes an input node, a first output node, a second output node, a number of capacitive elements, and a number of switching elements. The switching elements are coupled between the input node, the first output node, the second output node, and the capacitive elements. In operation, the switching elements charge and discharge the capacitive elements such that a power supply output voltage is provided asynchronously to the first output node and the second output node.

Circuitry includes a first RF power amplifier, a second RF power amplifier, a third RF power amplifier, a first bias signal generator, and a second bias signal generator. The first RF power amplifier and the second RF power amplifier are each configured to amplify RF signals for transmission in a first carrier network. The third RF power amplifier is configured to amplify RF signals for transmission in a second carrier network. In a first mode, the first bias signal generator provides a bias signal to the first RF power amplifier and the second bias signal generator provides a bias signal to the second RF power amplifier. In a second mode, the first bias signal generator and the second bias signal generator each provide a portion of a bias signal to the third RF power amplifier.

A reconfigurable load modulation amplifier having a first power amplifier (PA) configured to be supplied by a first drain voltage and a second PA coupled in parallel with the first PA, wherein the second PA is configured to be supplied by a second drain voltage is disclosed. The reconfigurable load modulation amplifier includes a quadrature coupler configured to combine power from both the first PA and the second PA for output through an output port. Also included is control circuitry configured to set at least one of the first drain voltage and the second drain voltage such that the first drain voltage is different than the second drain voltage. In at least one embodiment, the control circuitry is further configured to dynamically adjust at least one of the first drain voltage and the second drain voltage such that the first drain voltage is different than the second drain voltage.

A low noise amplifier (LNA) system having a constant noise factor (Const-NF) mode and a constant third-order intercept (Const-IP3) mode is disclosed. The LNA system includes an LNA core and a trade-off bias network coupled to the LNA core to selectably bias the LNA core to realize the Const-NF mode and the Const-IP3 mode. The trade-off bias network is made up of selectable Const-NF circuitry and selectable Const-IP3 circuitry. The LNA system further includes a bias switching controller that is configured to enable the selectable Const-NF circuitry and disable the selectable Const-IP3 circuitry to select the Const-NF mode in response to a first condition and to disable the selectable Const-NF circuitry and enable the selectable Const-IP3 circuitry to select the Const-IP3 mode in response to a second condition.

Apparatus and methods for reducing inductor ringing of a voltage converter are provided. In certain configurations, a voltage converter includes an inductor connected between a first node and a second node, a plurality of switches, and a bypass circuit having an activated state and a deactivated state. The switches includes a first switch connected between a battery voltage and the first node, a second switch connected between the first node and a ground voltage, a third switch connected between the second node and the ground voltage, and a fourth switch connected between the second node and the output. The bypass circuit includes a first pair of transistors connected between the first node and the second node and configured to turn on to bypass the inductor in the activated state and to turn off in the deactivated state.

In one aspect the embodiments relate to amplifier circuitry comprising an outphasing region and envelope tracking region. The outphasing region includes a signal processing block capable of receiving an amplitude and phase modulated input signal that is to be amplified, and processing said signal to separate it into two signals (S1, S2) of constant amplitude and modulated phase, a first signal S1 for driving a first RF power amplifier RF PA1 and a second signal S2 for driving a second RF power amplifier RF PA2. The output signals from each of the RF PAs are then provided to a power combiner (PC) for obtaining an output amplified signal (RF output). The envelope tracking region (100b) includes a linear amplifier (Env Amp) capable of receiving an input representing an envelope of the input signal that to be amplified, a charge storage device C1 coupled to said amplifier for providing an amplified envelope signal for driving the RF PAs, said amplifier (8) and charge storage device C1 being arranged to receive a supply voltage V+. The amplifier circuitry is configured such that when the first signal S1 and the second signal S2 in the outphasing circuit 100a are in phase, an input voltage V1 based on the voltage of the received envelope signal is provided to the amplifier in the envelope tracking region to enable the charge storage device C1 to supply a voltage V2 above the supply voltage V+ such that the output voltage of the RF PAs driven by the amplifier (8) is increased by V2 above the supply voltage V+.

A speaker driver comprising an amplifier, configured to receive a test signal that comprises a plurality of equivalent test-blocks, and provide measurement-signalling for a speaker at the amplifier output. The measurement-signalling comprising a plurality of measurement-blocks, wherein each of the measurement-blocks corresponds to the output of the amplifier for one of the plurality of test-blocks. The speaker driver also includes an output-current-sensor configured to: measure a current level of the measurement-signalling, and provide sensed-signalling that comprises a plurality of sensed-blocks, wherein each of the plurality of sensed-blocks corresponds to one of the plurality of measurement-blocks of the measurement-signalling. The speaker driver further includes a processor configured to either: (a) combine the plurality of sensed-blocks to provide a time-averaged-block; and determine a frequency-spectrum of the time-averaged-block; or (b) determine a frequency-spectrum of each of the plurality of sensed-blocks to provide a plurality of frequency-spectrum-sensed-blocks; and combine the plurality of frequency-spectrum-sensed-blocks to provide a time-averaged-frequency-spectrum-block.

An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.

Envelope tracking power converter circuitry is configured to receive a supply voltage and simultaneously provide a first envelope tracking power supply signal for amplifying a first RF input signal and a second envelope tracking signal for amplifying a second RF input signal.

The present invention relates to a differential envelope detector, which comprises: input terminals for separating cathode and anode components from a signal and receiving same; a first voltage output unit for outputting a first common mode voltage between the input terminals; a first amplification unit, which receives an input signal as a differential pair and amplifies same so as to output a first output signal; a second amplification unit, which receives the first common mode voltage so as to output a second output signal; and a second voltage output unit for outputting a second common mode voltage between a constant current source unit and an output terminal, wherein the output size of the detector is hardly affected by temperature changes, and an output DC voltage is also fixed so as to be effective with respect to input bias of the next stage amplifier.