A transmitter comprising a power amplifier, a phase modulator, a switched DC-DC converter, all operating in dual mode, and a controller is disclosed. The power amplifier is arranged to selectively operate either in a first mode or in a second mode, wherein the first mode is a linear mode and the second mode is a non-linear mode in order to save power with least increasing cost in hardware. The transmitter is adapted to operate at different allocated bandwidths, for different radio standards while keeping minimum power consumption governed by the controller. A transceiver, a communication device, a method and a computer program are also disclosed.

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.

A communication unit comprises a decimator configured to sample a variable control signal and output a reduced bandwidth variable control signal; and a multi-level power supply, MLPS, comprising an input and an output, wherein the input is coupled to the decimator and configured to receive the reduced bandwidth variable control signal and, in response thereto, the output delivers multi-level output voltages to supply a power amplifier, PA, module.

A power amplifier circuit including a power transistor, a variable impedance circuit, first and second envelope detecting circuits is provided. The power transistor receives an input signal and outputs an output signal. The variable impedance circuit includes an impedance control transistor and a first filter capacitor. An equivalent impedance of the variable impedance circuit varies with the input signal. The impedance control transistor is coupled to the power transistor and receives a control voltage. The first filter capacitor is coupled between the impedance control transistor and ground. Both the first and the second envelope detecting circuits detect the input signal to dynamically control the equivalent impedance of the variable impedance circuit.

An apparatus for controlling a pulse width modulation (PWM) amplifier is disclosed. In one aspect, the apparatus includes a delay circuit configured to delay an input signal and provide the delayed input signal to the PWM amplifier. The apparatus also includes a controller configured to generate and provide a supply voltage to the PWM amplifier based at least in part on the input signal such that the PWM amplifier generates an output signal based at least partially on the delayed input signal and the supply voltage.

A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.

Described embodiments provide an integrated power supply and modulator system. The system includes a magnetic regulation stage, a switched-capacitor voltage balancer stage, and at least one output switching stage. The switched-capacitor voltage balancer stage is coupled to an output of the magnetic regulation stage, and maintains a substantially ratiometric set of voltages with respect to a reference potential. The magnetic regulation stage includes an inductor and at least two switches to selectively couple the inductor to two or more of (a) an input of the magnetic regulation stage, (b) a first voltage node of the switched-capacitor voltage balancer stage, and (c) a second voltage node of the switched-capacitor voltage balancer stage. The output switching stage selectively couples at least two voltages from the switched-capacitor voltage balancer stage to an output of the system in response to control signals. The system may include startup circuitry, feedback/feedforward circuitry, and control circuitry.

Embodiments of the disclosure may include a method and apparatus for improving the efficiency and extending the operation time between recharges or replacement batteries of a portable audio delivery system. The audio delivery system may include a processor, an audio processing device, a speaker, and a rechargeable power source. The audio delivery system is generally configured to generate and/or receive an audio input signal and efficiently deliver an amplified, high quality audio output signal to a user. In some embodiments of the disclosure, the audio processing device of the audio delivery system may include a switch mode power supply (SMPS), a signal delay element, an envelope detector, and a switching signal amplifier.

A power amplifier module includes an amplifier transistor and a bias circuit. A first power supply voltage based on a first operation mode or a second power supply voltage based on a second operation mode is supplied to the amplifier transistor. The amplifier transistor receives a first signal and outputs a second signal obtained by amplifying the first signal. The bias circuit supplies a bias current to the amplifier transistor. The bias circuit includes first and second resistors and first and second transistors. The first transistor is connected in series with the first resistor and is turned ON by a first bias control voltage which is supplied when the first operation mode is used. The second transistor is connected in series with the second resistor and is turned ON by a second bias control voltage which is supplied when the second operation mode is used.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite.