A linearizer comprises a delay compensation circuit, an envelope reshaping circuit and a phase shift unit. The delay compensation circuit is configured to delay an input signal and to output a delayed input signal to a power amplifier. The envelope reshaping circuit is configured to detect an envelope of the input signal and to generate a reshaped envelope signal. The phase shift unit configured to provide an envelope reshaped capacitance based on the reshaped envelope signal to the delayed input signal to reshape the delayed input signal.

A power amplifier system having a carrier amplifier having a first supply node, a peaking amplifier having a second supply node, and envelope tracking (ET) circuitry is disclosed. The ET circuitry has a first tracking amplifier that generates a first voltage signal at the first supply node, a second tracking amplifier that generates a second voltage signal at the second supply node, and a transistor coupled between the first supply node and the second supply node. A control circuit has a first input coupled to an output of both or either of the first tracking amplifier and the second tracking amplifier and a control output terminal coupled to a control input terminal of the transistor, wherein the control circuit is configured to progressively turn on the transistor to pass current from the first supply node to the second supply node as the peaking amplifier progressively becomes active.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may transmit a capability message indicating a capability of the UE to perform bandwidth-limited envelope tracking or a capability of the UE to compensate for bandwidth-limited envelope tracking distortion. The UE may receive a request for the UE to activate bandwidth-limited envelope tracking or a request for the UE to compensate for bandwidth-limited envelope tracking distortion. In some examples, the UE may transmit an uplink message using a bandwidth-limited envelope tracking configuration. In other examples, the UE may receive a downlink message and use digital post distortion (DPoD) to correct bandwidth-limited envelope tracking distortions in the downlink message. Aspects of the present disclosure may enable the UE to use bandwidth-limited envelope tracking and DPoD for wideband signal transmissions, which may result in lower power consumption at the UE.

A multi-mode power management apparatus is provided. In embodiments disclosed herein, the multi-mode power management apparatus can be configured to operate in different power management modes across a wide range of modulation bandwidth (e.g., 80 KHz to over 200 MHz). The multi-mode power management apparatus includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC), which are implemented in separate dies. The PMIC is configured to generate a low-frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management apparatus can selectively output one or more of the ET voltages and the low-frequency voltage to different stages (e.g., driver stage and output stage) of a power amplifier circuit, thus helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide range of modulation bandwidth.

An APT module is provided that includes a converter circuit that outputs a power supply voltage, output terminals to which the power supply voltage is applied, a FB terminal connected to a signal path connecting the output terminal and power amplifiers, a FB terminal connected to a signal path connecting the output terminal and power amplifiers, and a control circuit connected to the FB terminals and the converter circuit.

A phase-reconfigurable circuit for a dual-input power amplifier is provided. The circuit includes an envelope detector configured to process an envelope of an RF input signal into an envelope signal. A first vector-sum phase-shifter and a second vector-sum phase-shifter processes an in-phase and a quadrature-phase version of the RF input signal with the envelope signal to produce a first differential output signal having a dynamically-modulated phase difference with a second differential output signal.

Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.

A radio frequency signal having a constant amplitude is modulated by a digital modulation signal and a radio frequency input signal whose amplitude changes stepwise is generated. The radio frequency input signal is input into a power amplifier that is an evaluation target. A period in which an amplitude of the radio frequency input signal is constant is defined as a measurement period and an output signal of the power amplifier is measured in each of measurement periods in which amplitudes of the radio frequency input signal are different from each other.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A radio frequency power amplifier, a chip, and a communication terminal. The radio frequency power amplifier comprises a power amplifier circuit (5), an output matching circuit (2), a power detection circuit (3), and a bias comparison circuit (4). The output power on a main signal path is measured by the power detection circuit (3), and an equivalent voltage proportional to the output power is obtained and input to the bias comparison circuit (4); the equivalent voltage value is adjusted by means of the bias comparison circuit (4) and compared with a control voltage (1) to provide a bias voltage and/or collector voltage for the power amplifier circuit (5), thereby forming a closed-loop circuit, such that the radio frequency power amplifier can work in a stable state when gains and output power are in different power levels.