A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.

A Doherty amplifier system is disclosed with a carrier amplifier configured to amplify a first portion of a radio frequency (RF) signal. A peaking amplifier with a peaking output is configured to amplify a second portion of the RF signal when it is above a power level threshold. A first inductor is coupled between the main output and a first middle node, and a second inductor is coupled between the first middle node and the peaking output. The first inductor and the second inductor are configured to have a first magnetic coupling to form a first impedance inverter. A third inductor is coupled between the peaking output and a second middle node, and a fourth inductor is coupled between the second middle node and an RF signal output. The third inductor and the fourth inductor are configured to have a second magnetic coupling to form a second impedance inverter.

An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.

Power amplifiers with adaptive bias for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The power amplifier includes a field-effect transistor (FET) for amplifying the RF signal, and a current mirror including an input that receives a reference current and an output connected to the power amplifier supply voltage. An internal voltage of the current mirror is used to bias the gate of the FET to compensate the FET for changes in the power amplifier supply voltage arising from envelope tracking.

Composite cascode power amplifiers for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a composite cascode power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The composite cascode power amplifier includes an enhancement mode (E-MODE) field-effect transistor (FET) for amplifying the RF signal and a depletion mode (D-MODE) FET in cascode with the E-MODE FET.

A method for powering an audio amplifier includes receiving an input audio signal in an audio signal processor, delaying the input audio signal in the audio signal processor to generate a delayed audio signal, predicting a power demand estimate by analyzing the input audio signal to calculate the power demand estimate in the audio signal processer, and selecting, by the audio signal processor, power conversion settings for a DC to DC converter on the basis of the power demand estimate. The method further includes supplying power input to the DC to DC converter, converting the power input in accordance with the power conversion settings to provide a power output, powering the audio amplifier using the power output, and supplying the delayed audio signal to the audio amplifier from the audio signal processor to generate an amplified audio signal.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

The present disclosure relates to a dual-modulation power management circuit (PMC), which includes a first tracking amplifier coupled to a first voltage port and configured to contribute to a first modulated voltage at the first voltage port, a second tracking amplifier coupled to a second voltage port and configured to contribute to a second modulated voltage at the second voltage port, a charge pump, a power inductor, and a low-dropout (LDO) switch unit. Herein, the power inductor is configured to induce an output current, which is based on a boosted voltage generated by the charge pump, toward the first voltage port. A first portion of the output current is eligible to flow through the LDO switch unit from the first voltage port to the second voltage port. The first modulated voltage is not smaller than the second modulated voltage over time.

Envelope tracking systems for power amplifiers are provided herein. In certain embodiments, an envelope tracker supplies power to a power amplifier that amplifies an RF signal. The envelope tracker includes a multi-level switching circuit that generates an output current based on an envelope signal indicating an envelope of the RF signal. The envelope tracker further includes a combiner that combines a DC voltage with the output current of the multi-level switching circuit to generate a power amplifier supply voltage for the power amplifier. Accordingly, the output current of the multi-level switching circuit and a DC voltage are combined to generate the power amplifier supply voltage. Implementing the envelope tracking system in this manner can provide enhanced efficiency and/or higher bandwidth relative to an envelope tracking system in which a multi-level switching circuit directly outputs a power amplifier supply voltage.

A signal envelope detector is provided. The signal envelope detector includes an input node configured to receive an input signal. Further, the signal envelope detector includes a capacitive voltage divider coupled to the input node and configured to generate an attenuated input signal by voltage division of the input signal. The signal envelope detector additionally includes a source follower transistor coupled between a first node configured to receive a first voltage supply signal and a second node configured to receive a second voltage supply signal. A gate terminal of the source follower transistor is coupled to the capacitive voltage divider and configured to receive the attenuated input signal. The signal envelope detector includes a rectifier circuit configured to receive and rectify an output signal of the source follower transistor. In addition, the signal envelope detector includes a low-pass filter coupled to the rectifier circuit and configured to generate an envelope signal indicative of a rectified envelope of the input signal by low-pass filtering of an output signal of the rectifier circuit.