A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

An envelope tracking (ET) power management apparatus incorporating multiple power amplifiers is provided. The ET power management apparatus includes a single ET integrated circuit (ETIC) configured to provide multiple ET voltages to the multiple power amplifiers for amplifying a radio frequency (RF) signal concurrently. The ETIC includes multiple first ET voltage circuits configured to generate multiple first ET voltages and a second ET voltage circuit configured to generate a second ET voltage. The ETIC is configured to provide each of the first ET voltages to an output stage amplifier(s) in a respective one of the power amplifiers and provide the second ET voltage to a driver stage amplifier in all of the power amplifiers. By supporting the multiple power amplifiers using a single ETIC, it is possible to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ET power management apparatus.

Equalizer circuitry includes a differential target voltage input, an equalizer output, a first operational amplifier, and a second operational amplifier. The differential target voltage input includes a target voltage input node and an inverted target voltage input node. The first operational amplifier and the second operational amplifier are coupled in series between the differential target voltage input and the equalizer output. The first operational amplifier is configured to receive a target voltage signal and provide an intermediate signal based on the target voltage input signal. The second operational amplifier is configured to receive the intermediate signal and an inverted target voltage signal and provide an output signal to the equalizer output. The first operational amplifier and the second operational amplifier are interconnected with one or more passive components such that a transfer function between the differential target voltage input and the equalizer output is a second-order complex-zero function.

A distributed envelope tracking (ET) amplifier circuit and related apparatus are provided. The distributed ET amplifier apparatus includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage. In examples discussed herein, the amplifier circuit is co-located with an ET voltage circuit configured to supply the modulated voltage such that a trace inductance between the amplifier circuit and the ET voltage circuit can be reduced to below a defined threshold. By co-locating the amplifier circuit with the ET voltage circuit to reduce a coupling distance between the amplifier circuit and the ET voltage circuit and thus the trace inductance associated with the coupling distance, it may be possible to reduce degradation in the modulated voltage. As a result, it may be possible to improve efficiency and maintain linearity in the amplifier circuit, particularly when the RF signal is modulated at a higher modulation bandwidth.

Disclosed are systems, devices, modules, methods, and other implementations, including a method for digital predistortion that includes receiving, by a digital predistorter, a first signal that depends on amplitude variations based on an input signal, u, with the variations of the first signal corresponding to time variations in non-linear characteristics of a transmit chain that includes a power amplifier. The method further includes receiving, by the digital predistorter, the input signal u, generating, by the digital predistorter, based at least in part on signals comprising the input signal u and the first signal, a digitally predistorted signal v to mitigate the non-linear behavior of the transmit chain, and providing the predistorted signal v to the transmit chain.

An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.

An integrated circuit that includes a die with an active radio frequency (RF) unit embedded thereon; a first port for receiving an output signal from the active RF unit; a harmonic filter that comprises a first harmonic filter inductor; and a first RF inductive load that is electrically coupled to the first port and is magnetically coupled to the first harmonic filter inductor.

A voltage generation circuit and related envelope tracking (ET) amplifier apparatus is provided. In examples discussed herein, a voltage generation circuit can be provided in an ET amplifier apparatus to provide a supply voltage to a voltage amplifier(s) that is configured to generate an ET voltage for an amplifier circuit(s). In a non-limiting example, the voltage amplifier(s) receives an ET target voltage signal corresponding to a time-variant target voltage envelope and generates the ET voltage conforming to the time-variant target voltage envelope. The voltage generation circuit is configured to generate one or more supply voltages and selectively provide one of the supply voltages to the voltage amplifier(s) in accordance to the time-variant target voltage envelope. By selectively providing the supply voltage based on the time-variant target voltage envelope, it may be possible to improve efficiency of the voltage amplifier, thus helping to improve efficiency and linearity of the amplifier circuit(s).

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.