Multi-level envelope trackers with an analog interface are provided herein. In certain embodiments, an envelope tracking system for generating a power amplifier supply voltage for a power amplifier is provided. The envelope tracking system includes a multi-level supply (MLS) DC-to-DC converter that outputs multiple regulated voltages, and an MLS modulator that controls selection of the regulated voltages over time based on an analog envelope signal corresponding to an envelope of the RF signal amplified by the power amplifier.

An audio signal amplifying device processes an input signal to provide an output signal for a balanced headphone. The device includes a signal detection circuit, a voltage supply circuit, and an amplifying circuit. The signal detection circuit detects the variation in the input signal to generate a detection result. The voltage supply circuit outputs one of multiple voltages as a supply voltage according to the detection result; when the detection result indicates the amplitude of the input signal satisfying a first condition, the supply voltage is a first voltage; when the detection result indicates the amplitude of the input signal satisfying a second condition, the supply voltage is a second voltage lower than the first voltage; and the amplitude satisfying the first condition is greater than the amplitude satisfying the second condition. The amplifying circuit generates the output signal according to the input signal based on the supply voltage.

A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

An amplifier circuit includes power amplifiers, trackers capable of outputting a variable power supply voltage, a switch connected between an output port of the tracker and an output port of the tracker, and a switch connected between the output port of the tracker and the power amplifier, and the output port of the tracker is connected to the power amplifier.

A switching system is connected to the power amplifier of an RF system. The switching system can switch the DC supply voltage to the power amplifier while handling the high DC current and the nanosecond switching speed requirements that are mandatory for most RF systems. The embodiments can rapidly control DC voltages but not interfere with the optimized operation of the RF transistor. The embodiments provide a desired sharp turn-on leading edge for an RF pulse while eliminating the extremely long and undesirable ramp down that typically occurs beyond the desired RF pulse period.

A power amplifier circuit includes external input and output terminals; a first power amplifier with first input and output terminals, the first input terminal being connected to the external input terminal, the first output terminal being connected to the external output terminal; a second power amplifier having second input and output terminals, the second input terminal being connected to the external input terminal, the second output terminal being connected to the external output terminal; a power supply terminal that receives a power supply voltage that is supplied to the first power amplifier and controllably supplied to the second power amplifier; and a switch having first and second terminals, the first terminal being connected to the power supply terminal, the second terminal being connected to the second power amplifier.

A power amplifier circuit includes an amplifier transistor having a collector terminal, an emitter terminal, and a base terminal, bias circuits, and a current limiter circuit. The bias circuit includes a constant current amplifier transistor that supplies direct-current bias current from an emitter terminal to the base terminal. The current limiter circuit includes a current limiting transistor an emitter terminal of which is connected to the bias circuit, a resistive element connected between the current limiting transistor and a power supply terminal, and a resistive element connected between the current limiting transistor and the constant current amplifier transistor. The bias circuit includes a constant current amplifier transistor that supplies direct-current bias current i3 from an emitter terminal to the base terminal.

A power amplifier includes a power transistor configured to amplify an input radio-frequency (RF) signal, and a bias circuit configured to provide a bias current to the power transistor, and in a first power mode, detect a first signal corresponding to a first level or more in the input RF signal and generate the bias current corresponding to the first signal, or detect a second signal corresponding to a second level or less in the input RF signal and generate the bias current corresponding to the second signal, and in a second power mode, detect a third signal corresponding to a third level or more in the input RF signal and generate the bias current corresponding to the third signal, or detect a fourth signal corresponding to a fourth level or less in the input RF signal and generate the bias current corresponding to the fourth signal.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An envelope detecting circuit is for generating an envelope signal of an input RF signal as described. The envelope detecting circuit includes an input terminal, an output terminal, a balun, a transistor, and an integrating circuit. The transistor, which is operated in the class B or the class C mode, receives an input signal from the balun, amplifies the input signal, and outputs an amplified signal. The integrating circuit, which is provided between the transistor and the output terminal, provides a series circuit of a resistor and a capacitor between the bias supply and ground. The transistor receives the bias through the resistor. The capacitor holds bottom levels of the amplified signal.