A distributed amplifier includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a first common-gate configured transistor coupled to the output transmission circuit, a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor, and a second common-gate configured transistor coupled between the first common-gate configured transistor and common-source configured transistor.

A power amplification circuit that includes: a capacitor element in which a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer are sequentially stacked, the capacitor element including a first capacitor in which the first metal layer serves as one electrode thereof and the second metal layer serves as another electrode thereof, and a second capacitor in which the second metal layer serves as one electrode thereof and the third metal layer serves as another electrode thereof; and a transistor that amplifies a radio-frequency signal. The radio-frequency signal is supplied to the one electrode of the first capacitor. The other electrode of the first capacitor and the one electrode of the second capacitor are connected to a base of the transistor, and the other electrode of the second capacitor is connected to the emitter of the transistor.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

A common-source Low Noise Amplifier (LNA) comprises a first spiral inductor coupled to a source of a first transistor, a second spiral inductor coupled to a drain of a second transistor, and a third inductor connecting the first transistor to the second transistor. The third inductor is configurable to enable a first capacitance to be coupled in parallel to form a bandpass filter. The first spiral inductor is configurable to enable a second capacitance to be coupled in parallel to form a resonant circuit. A variation of the LNA further includes a drain of a third transistor coupled to a gate of a fourth transistor with a first width, a source of the third transistor coupled to the resonant circuit, and an oscillator clock configured to operate at a first frequency that enables the third transistor, wherein the third transistor presents a first impedance to the resonant circuit, causing the resonant circuit to have a first bandwidth.

A device includes a substrate and a package input terminal. The device includes a driver amplifier mounted to the substrate and configured to receive a radio frequency input signal. A first amplifier is mounted to the substrate. The first amplifier includes a first amplifier input terminal. A second amplifier is mounted to the substrate. The second amplifier includes a second amplifier input terminal. An inter-stage network is connected between the driver amplifier and the first amplifier and between the driver amplifier and the second amplifier. The inter-stage network includes a first capacitor connected between the driver amplifier and the first amplifier input terminal, and an inductor having a first terminal and a second terminal. The first terminal of the inductor is connected to the first capacitor. The inter-stage network includes a second capacitor connected between the second terminal of the inductor and the second amplifier input terminal.

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

The present disclosure relates to a power amplifier (PA) system provided in a semiconductor device and having feed forward gain control. The PA system comprises a transmit path and control circuitry. The transmit path is configured to amplify an input radio frequency (RF) signal and comprises a first tank circuit and a PA stage. The control circuitry is configured to detect a power level associated with the input RF signal and control a first bias signal provided to the PA stage based on a first function of the power level and control a quality factor (Q) of the first tank circuit based on a second function of the power level.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.

Disclosed are systems, devices, and methodologies to reduce harmonics in a radio frequency output signal. A power amplifier system comprises a power amplifier and a tunable output matching network electrically connected between the output of the power amplifier and an output of the tunable output matching network. The tunable output matching network reduces second-order harmonics in an amplified radio frequency signal when the power amplifier operates in a low frequency mode. The tunable output matching network includes traps such as a series inductor and a first capacitor in series with a first switch, a second capacitor in series with a second switch, and a third capacitor in series with a third switch, where the traps are tuned to selected harmonic frequencies when the power amplifier operates in the low frequency band of the operating band of frequencies.