H03F2200/12

Power source supply circuit, amplifier, communication device, base station, and power source supply method
10361693 · 2019-07-23 · ·

A power source supply circuit includes: a plurality of power sources (11-1, 11-2) that generate power source voltages different from each other; a switch circuit (14) that switches and outputs the power source voltages generated in the plurality of power sources (11-1, 11-2); a voltage output terminal (16) that outputs outside the power source voltages output from the switch circuit (14); an RF choke circuit (15) provided between the switch circuit (14) and the voltage output terminal (16), the RF choke circuit (15) including a first capacitor; and a second capacitor (12-1, 12-2) provided between the plurality of power sources (11-1, 11-2) and the switch circuit (14), the second capacitor (12-1, 12-2) having a larger capacitance than the first capacitor.

Controlling a power amplification stage of an audio signal amplifier
10361672 · 2019-07-23 · ·

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.

Semiconductor device

A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).

BIASED AMPLIFIER
20190115885 · 2019-04-18 ·

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

Driver with distributed architecture

A distributed driver for an optic signal generator has a first amplifier cell with one or more amplifiers configured to receive and amplify an input signal to create a first amplified signal. A second amplifier cell has one or more amplifiers configured to receive and amplify the input signal to create a second amplified signal. A first conductive path and second conductive path connects to the first amplifier cell and the second amplifier cell such that the inductance associated with the first and second conductive path counteracts a capacitance associated with the first amplifier cell and the second amplifier cell. A variable capacitor may be part of the first amplifier cell and/or the second amplifier cell to selectively tune the capacitance of the distributed driver. A distributed bias circuit may be part of the first amplifier cell and/or the second amplifier cell to bias an optic signal transmitter.

DISTRIBUTED CIRCUIT AND CONTROL METHOD THEREFOR
20240235507 · 2024-07-11 ·

A distributed circuit includes: a first transmission line that has an input end to which an input signal is input; a second transmission line that has an output end from which an output signal is output; a plurality of unit cells that are disposed along the first and second transmission lines, the input terminals of the unit cells being connected to the first transmission line, the output terminals of the unit cells being connected to the second transmission line; two input termination resistors connected in parallel to an end of the first transmission line; and two output termination resistors connected in parallel to an end of the second transmission line. In the distributed circuit, at least one input termination resistor is a temperature-gradient resistor, and voltages at the two input termination resistors are changed symmetrically.

Controlling a Power Amplification Stage of an Audio Signal Amplifier
20180287579 · 2018-10-04 ·

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.

MULTI-MODE POWER AMPLIFIER
20180234061 · 2018-08-16 ·

A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit.

Controlling a power amplification stage of an audio signal amplifier
10014840 · 2018-07-03 · ·

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.

Low voltage supply amplifier
09998080 · 2018-06-12 · ·

A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.