An active biconical antenna and a receive array comprising a combination of active biconical and Vivaldi antennas. In one configuration, the active biconical antenna includes upper and lower cones. Each cone has a respective truncated apex. First and second feed points are respectively connected to the truncated apexes of the upper and lower cones and to first and second conductors. The active biconical antenna further includes a buffer amplifier having respective input terminals connected to the first and second conductors. The buffer amplifier has an input impedance that is impedance matched to an antenna impedance at and above but not below a frequency f.sub.c and is higher than the antenna impedance at frequencies substantially less than f.sub.c. The buffer amplifier also has an output impedance that is impedance matched to a system impedance at frequencies both above and below f.sub.c. A length of the first and second conductors is less than a wavelength at the frequency f.sub.c.

An active biconical antenna and a receive array comprising a combination of active biconical and Vivaldi antennas. In one configuration, the active biconical antenna includes upper and lower cones. Each cone has a respective truncated apex. First and second feed points are respectively connected to the truncated apexes of the upper and lower cones and to first and second conductors. The active biconical antenna further includes a buffer amplifier having respective input terminals connected to the first and second conductors. The buffer amplifier has an input impedance that is impedance matched to an antenna impedance at and above but not below a frequency f.sub.c and is higher than the antenna impedance at frequencies substantially less than f.sub.c. The buffer amplifier also has an output impedance that is impedance matched to a system impedance at frequencies both above and below f.sub.c. A length of the first and second conductors is less than a wavelength at the frequency f.sub.c.

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.

A close-down pop reduction system and a method for close-down pop reduction in an audio amplifier assembly are disclosed. The switching power conversion system comprises a forward path having a compensator and a switching power stage and a signal path from an output of a comparator in the switching power stage to a sequence control unit. The signal path includes a close-down timing circuit configured to provide a timing signal. The sequence control unit is configured to eliminate the input signal, increase the switch frequency of the close-down pop reduction system and disable the switching power stage at a moment in time within a PWM pulse of the switching power stage. Hereby, it is e.g. possible to minimize the audible pop during close-down of audio amplifier assemblies.

According to an embodiment, a circuit includes a high-Ω resistor including a plurality of semiconductor junction devices coupled in series and a plurality of additional capacitances formed in parallel with the plurality of semiconductor junction devices. Each semiconductor junction device of the plurality of semiconductor junction devices includes a parasitic doped well capacitance configured to insert a parasitic zero in a noise transfer function of the high-Ω resistor. Each additional capacitance of the plurality of additional capacitances is configured to adjust a parasitic pole in the noise transfer function of the high-Ω resistor in order to compensate for the parasitic zero.

A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.

An analog front-end circuit capable of dynamically adjusting gain includes a programmable gain amplifier (PGA) circuit, a sensor, a calculation circuit, a gain coarse control circuit and a gain fine control circuit. The PGA circuit includes an amplifier, a gain coarse adjustment circuit and a gain fine adjustment circuit. The gain coarse adjustment circuit is controlled by a coarse control signal, and a gain is adjusted in a coarse step according to an initial gain. The gain fine adjustment circuit is controlled by a fine control signal in a data mode, and the gain is adjusted in a fine step. The calculation circuit calculates a primary gain adjustment and a secondary gain adjustment. The gain coarse control circuit generates the coarse control signal according to the primary gain adjustment, and the gain fine control circuit generates the fine control signal according to the secondary gain adjustment.

A high bandwidth continuous time linear equalization (HBCTLE) circuit is disclosed. The HBCTLE circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit. A feedback circuit is coupled between the output of the CTLE circuit and an output of the gain circuit.

A solid-state imaging device includes M pixel units to and a correction unit. The pixel unit includes a main amplifier, a capacitive element, a first switch, a second switch, a photodiode, a feedback capacitive element, and an initialization switch. The correction unit includes a null amplifier, a capacitive element, a first switch, and a second switch. An effective offset voltage of the main amplifier is small.