Methods of calibrating a power amplifier system to compensate for envelope amplitude misalignment are provided. In certain configurations, a method of calibrating a power amplifier system includes amplifying a radio frequency signal from a transceiver using a power amplifier and generating a supply voltage of the power amplifier using an envelope tracker, including generating a scaled envelope signal based on a power control level signal and an envelope signal, and shaping the scaled envelope signal using a shaping table generated at a target gain compression. The method further includes changing a scaling of the scaled envelope signal using a calibration module, monitoring an output of the power amplifier to determine an amount of scaling of the scaled envelope signal at which a detected gain compression of the power amplifier corresponds to the target gain compression of the shaping table, and calibrating the power amplifier system based on the determination.

A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input signal of the transistor circuit to a gate bias voltage and to apply the gate bias voltage to the gate terminal of the transistor, a second circuit configured to convert the AC input signal of the transistor circuit to a control voltage, and a switching circuit configured to apply a first voltage to the first conduction terminal of the transistor in response to the control voltage.

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.

A linearization circuit reduces intermodulation distortion in an amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the amplifier.

A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.

A system includes an input port having an input voltage, an output port having an output voltage, and a power converter having a switch network with a plurality of power switches and a first resonant tank having a first resonant capacitor and a first resonant inductor, where at least one resonant component within the first resonant capacitor and the first resonant inductor is a switchable component configured to switch between different values. The system further includes a resonant mode selection block configured to adjust a value of the switchable component to maintain a performance of the system, and a controller configured to adjust a switching frequency or a duty cycle of the power converter.

Embodiments of the present disclosure provide circuitry and a method for a gallium nitride (GaN) device. The circuitry includes a negative bias circuit configured to provide a negative bias voltage for a gate of the GaN device; a drain switch circuit configured to turn on or off a positive voltage for a drain of the GaN device; and a control circuit configured to control the drain switch circuit based on provision of the negative bias voltage, such that the positive voltage for the drain is turned on after a voltage of the gate reaches the negative bias voltage and turned off before the negative bias voltage completely disappears.

A device to drive a plurality of power switches in a power converter with an input voltage port having an input voltage includes a drive resonant tank, a switch network, a control block configured to control the turn-on and turn-off of drive switches, and an output port. The drive resonant tank has a resonant inductor, and a resonant capacitor which includes an input capacitance of a power switch. The switch network has a plurality of drive switches, which are controlled such that the drive resonant tank goes through a resonant state and a pseudo clamp state consecutively during a switching period. A gate drive voltage of a power switch fluctuates slightly during the pseudo clamp state. The output port has two terminals coupled to a gate and a source of a power switch respectively.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

A linearization circuit reduces intermodulation distortion in an amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the amplifier.