This invention relates to a self-excited oscillation suppression device and method for the power amplifying circuit, belonging to the field of electronic technology. Said power amplifying circuit includes a FET and a feedback loop. Said device includes: a first compensation circuit which is connected between a drain and a gate of the FET and a second compensation circuit which is connected in parallel with a feedback resistor of said feedback loop. It can solve self-excited oscillation caused by deep negative feedback in the existing power amplifying circuit. The first compensation circuit can shift the open-loop gain curve forward as a whole, and the second compensation circuit can speed up the closure of the feedback gain curve and the open-loop gain curve so that the two curves will close up before the self-excited oscillation; the self-excited oscillation will be suppressed, and the stability of the power amplifying circuit will be improved.

An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

A tunable impedance multiplier with high multiplication factor is described. A single externally connected resistor is used and the multiplier is free of passive elements. The circuit can realize a positive or a negative impedance multiplier. Applications of the design to low and high pass filters are also presented. The simulation and experimental results show that the new design enjoys a multiplication factor above 400 at 2 Hz-to 7 MHz.

In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.

In accordance with an embodiment, a circuit includes: a first super source follower; a compensation circuit having a compensating node configured to provide a voltage of opposite phase of a voltage of an internal node of the first super source follower; and a first compensation capacitor coupled between an input of the first super source follower and the compensating node of the compensation circuit.

An amplifier circuit comprising: a power amplifier; a bias control circuit coupled to the power amplifier and having a voltage sensor configured to sense a bias voltage to the power amplifier, the bias control circuit being configured to determine whether the bias voltage exceeds a threshold voltage; and a protection circuit coupled to the power amplifier, the bias control circuit being further configured to control the protection circuit to apply a clamping status to limit a power output of the power amplifier to a predetermined value in response to the bias control circuit determining that the bias voltage exceeds a threshold voltage.

Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.

An amplifying circuit including a first gain circuit, a second gain circuit, a Miller capacitor, a positive feedback circuit and a feedforward gain circuit. The second gain circuit is configured to receive a first gain signal from the first gain circuit and generate a second gain signal. The Miller capacitor, the positive feedback circuit and the feedforward gain circuit are electrically coupled between an input terminal and an output terminal of the second gain circuit. The positive feedback circuit is configured to feedback the signal of the output terminal of the second gain circuit to the input terminal of the second gain circuit. The feedforward gain circuit is configured to amplify the first gain signal to output a third gain signal to the output terminal of the second gain circuit.

Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.